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" On-chip networks / "
Natalie Enright Jerger, Li-Shiuan Peh.
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BL
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| Record Number
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1018296
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b772666
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| Main Entry
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Enright Jerger, Natalie D.
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| Title & Author
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On-chip networks /\ Natalie Enright Jerger, Li-Shiuan Peh.
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| Publication Statement
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[San Rafael, Calif.] :: Morgan & Claypool Publishers,, ©2009.
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| Series Statement
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Synthesis lectures on computer architecture,; #8
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| Page. NO
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1 online resource (xii, 127 pages) :: illustrations
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| ISBN
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1598295853
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: 9781598295856
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1598295845
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9781598295849
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| Bibliographies/Indexes
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Includes bibliographical references (pages 105-125).
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| Contents
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Introduction -- The advent of the multi-core era -- Communication demands of multi-core architectures -- On-chip vs. off-chip networks -- Network basics: a quick primer -- Evolution to on-chip networks -- On-chip network building blocks -- Performance and cost -- Commercial on-chip network chips -- This book -- Interface with system architecture -- Shared memory networks in chip multiprocessors -- Impact of coherence protocol on network performance -- Coherence protocol requirements for the on-chip network -- Protocol-level network deadlock -- Impact of cache hierarchy implementation on network performance -- Home node and memory controller design issues -- Miss and transaction status holding registers -- Synthesized NoCs in MPSoCs -- The role of application characterization in NoC design -- Design requirements for on-chip network -- NoC synthesis -- NoC network interface standards -- Bibliographic notes -- Case studies -- Brief state-of-the-art survey -- Topology -- Metrics for comparing topologies -- Direct topologies: rings, meshes and Tori -- Indirect topologies: butterflies, Clos networks and fat trees -- Irregular topologies -- Splitting and merging -- Topology synthesis algorithm example -- Layout and implementation -- Concentrators -- Implication of abstract metrics on on-chip implementation -- Bibliographic notes -- Case studies -- Brief state-of-the-art survey -- Routing -- Types of routing algorithms -- Deadlock avoidance -- Deterministic dimension-ordered routing -- Oblivious routing -- Adaptive routing -- Adaptive turn model routing -- Implementation -- Source routing -- Node table-based routing -- Combinational circuits -- Adaptive routing -- Routing on irregular topologies -- Bibliographic notes -- Case studies -- Brief state-of-the-art survey -- Flow control -- Messages, packets, flits and phits -- Message-based flow control -- Circuit switching -- Packet-based flow control -- Store and forward -- Cut-through -- Flit-based flow control -- Wormhole -- Virtual channels -- Deadlock-free flow control -- Escape VCs -- Buffer backpressure -- Implementation -- Buffer sizing for turnaround time -- Reverse signaling wires -- Flow control implementation in MPSoCs -- Bibliographic notes -- Case studies -- Brief state-of-the-art survey -- Router microarchitecture -- Virtual channel router microarchitecture -- Pipeline -- Pipeline implementation -- Pipeline optimizations -- Buffer organization -- Switch design -- Crossbar designs -- Crossbar speedup -- Crossbar slicing -- Allocators and arbiters -- Round-robin arbiter -- Matrix arbiter -- Separable allocator -- Wavefront allocator -- Allocator organization -- Implementation -- Router floorplanning -- Buffer implementation -- Bibliographic notes -- Case studies -- Brief state-of-the-art survey -- Conclusions -- Gap between state-of-the-art and ideal -- Definition of ideal interconnect fabric -- Definition of state-of-the-art -- Network power-delay-throughput gap -- Key research challenges -- Low-power on-chip networks -- Beyond conventional interconnects -- Resilient on-chip networks -- NoC infrastructures -- On-chip network benchmarks -- On-chip networks conferences -- Bibliographic notes.
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| Abstract
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With the ability to integrate a large number of cores on a single chip, research into on-chip networks to facilitate communication becomes increasingly important. On-chip networks seek to provide a scalable and high-bandwidth communication substrate for multi-core and many-core architectures. High bandwidth and low latency within the on-chip network must be achieved while fitting within tight area and power budgets. In this lecture, we examine various fundamental aspects of on-chip network design and provide the reader with an overview of the current state-of-the-art research in this field.
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| Subject
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Networks on a chip.
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| Subject
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COMPUTERS-- Hardware-- Mainframes Minicomputers.
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Networks on a chip.
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| Dewey Classification
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004.1
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| LC Classification
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TK5105.546
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| Added Entry
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Peh, Li-Shiuan.
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