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" Logic-timing simulation and the degradation delay model / "
Manuel J. Bellido, Jorge Juan, Manuel Valencia.
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BL
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| Record Number
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1032169
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b786539
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| Main Entry
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Bellido, Manuel J.,1964-
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| Title & Author
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Logic-timing simulation and the degradation delay model /\ Manuel J. Bellido, Jorge Juan, Manuel Valencia.
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| Publication Statement
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London :: Imperial College Press,, ©2006.
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| Page. NO
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1 online resource (xvii, 267 pages) :: illustrations
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| ISBN
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1860945899
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: 1860947360
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: 9781860945892
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: 9781860947360
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Includes bibliographical references and index.
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| Abstract
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This book provides the reader with an extensive background in the field of logic-timing simulation and delay modeling. It includes detailed information on the challenges of logic-timing simulation, applications, advantages and drawbacks. The capabilities of logic-timing are explored using the latest research results that are brought together from previously disseminated materials. An important part of the book is devoted to the description of the "Degradation Delay Model", developed by the authors, showing how the inclusion of dynamic effects in the modeling of delays greatly improves the appl.
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| Subject
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Computer simulation.
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Mathematical models.
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Computer simulation.
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COMPUTERS-- Computer Simulation.
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Mathematical models.
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| Dewey Classification
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003.3
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| LC Classification
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TK7868.T5B45 2006eb
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| Added Entry
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Juan Chico, Jorge.
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Valencia, Manuel.
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