| Document Type
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BL
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| Record Number
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1045513
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| Doc. No
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b799883
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| Main Entry
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Veendrick, H. J. M., (Harry J. M.)
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| Title & Author
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Nanometer CMOS ICs : : from basics to ASICs /\ Harry Veendrick.
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| Edition Statement
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1st English ed.
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| Publication Statement
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Heidelberg ;New York :: Springer,, 2008.
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| Page. NO
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1 online resource (xxxii, 730 pages) :: illustrations (some color)
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| ISBN
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1402083327
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: 1402083335
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: 9781402083327
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: 9781402083334
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| Bibliographies/Indexes
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Includes bibliographical references and index.
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| Contents
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Title Page; Copyright Page; Foreword; Preface; Overview of symbols; List of physical constants; Table of Contents; Chapter 1 Basic Principles; 1.1 Introduction; 1.2 The field-effect principle; 1.3 The inversion-layer MOS transistor; 1.3.1 The Metal-Oxide-Semiconductor (MOS) capacitor; 1.3.2 The inversion-layer MOS transistor; 1.4 Derivation of simple MOS formulae; 1.5 The back-bias effect (back-gate effect, body effect) and the effect of forward-bias; 1.6 Factors which characterise the behaviour ofthe MOS transistor; 1.7 Different types of MOS transistors; 1.8 Parasitic MOS transistors.
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1.9 MOS transistor symbols1.10 Capacitances in MOS structures; 1.11 Conclusions; 1.12 References; 1.13 Exercises; Chapter 2 Geometrical-, physical- and field-scaling impact on MOS transistor behaviour; 2.1 Introduction; 2.2 The zero field mobility; 2.3 Carrier mobility reduction; 2.3.1 Vertical and lateral field carrier mobility reduction; 2.3.2 Stress-induced carrier mobility effects; 2.4 Channel length modulation; 2.5 Short- and narrow-channel effects; 2.5.1 Short-channel effects; 2.5.2 Narrow-channel effect; 2.6 Temperature influence on carrier mobility and threshold voltage.
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2.7 MOS transistor leakage mechanisms2.7.1 Weak-inversion (subthreshold) behaviour of the MOS transistor; 2.7.2 Gate-oxide tunnelling; 2.7.3 Reverse-bias junction leakage; 2.7.4 Gate-induced drain leakage (GIDL); 2.7.5 Impact Ionisation; 2.7.6 Overall leakage interactions and considerations; 2.8 MOS transistor models; 2.9 Conclusions; 2.10 References; 2.11 Exercises; Chapter 3 Manufacture of MOS devices; 3.1 Introduction; 3.2 Different substrates (wafers) as starting material; 3.2.1 Wafer sizes; 3.2.2 Standard CMOS Epi; 3.2.3 Crystalline orientation of the silicon wafer.
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3.2.4 Silicon-an-insulator (SOl)3.3 Lithography in MOS processes; 3.3.1 Lithography basics; 3.3.2 Lithographic alternatives beyond 40 nrn; 3.3.3 Next generation lithography; 3.3.4 Mask cost reduction techniques for low-volume production; Pattern imaging; 3.4 Etching; 3.5 Oxidation; 3.6 Deposition; 3.7 Diffusion and ion implantation; Diffusion; Ion Implantation; 3.8 Planarisation; 3.9 Basic MOS technologies; 3.9.1 The basic silicon-gate nMOS process; 3.9.2 The basic Complementary MOS (CMOS) process; 3.9.3 An advanced nanometer CMOS process; Shallow-trench isolation; Retrograde-well formation.
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Drain extensionSilicides, polycides and salicides; Ti/TiN film; Anti-Reflective Coating (ARC); Contact (re)fill; Damascene metal patterning; 3.9.4 CMOS technology options beyond 45nm; Devices; Interconnects; 3.10 Conclusions; 3.11 References; 3.12 Exercises; Chapter 4 CMOS circuits; 4.1 Introduction; 4.2 The basic nMOS inverter; 4.2.1 Introduction; 4.2.2 The DC behaviour; Saturated enhancement load transistor; The non-saturated enhancement load transistor; The depletion load transistor; The resistive load; 4.2.3 Comparison of the different nMOS inverters.
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| Abstract
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CMOS technologies account for almost 90% of all integrated circuits (ICs). This book provides an essential introduction to nanometer CMOS ICs. The contents of this book are based upon several previous publications and editions entitled 'MOS ICs' and 'Deep-Submicron CMOS ICs'. Nanometer CMOS ICs is fully updated and is not just a copy-and-paste of previous material. It includes aspects of scaling up to and beyond 32nm CMOS technologies and designs. It clearly describes the fundamental CMOS operating principles and presents substantial insight into the various aspects of design implementation and application. In contrast to other works on this topic, the book explores all associated disciplines of nanometer CMOS ICs, including physics, design, technology, yield, packaging, less-power design, variability, reliability and signal integrity. Finally it also includes extensive discussions on the trends and challenges for further scaling. The text is based upon in-house Philips and NXP Semiconductors courseware, which, to date, has been completed by more than 3000 engineers working in a large variety of related disciplines: architecture, design, test, process, packaging, failure analysis and software. Carefully structured and enriched by in-depth exercises, hundreds of colour figures and photographs and many references, the book is well-suited for the purpose of self-study.
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| Subject
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Application-specific integrated circuits.
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Metal oxide semiconductors, Complementary.
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Application-specific integrated circuits.
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Ingénierie.
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Metal oxide semiconductors, Complementary.
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| Dewey Classification
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621.39732
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| LC Classification
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TK7871.99.M44V45 2008
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