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" Design, Prototyping, and System-Level Analysis of a Novel Light Emitting Diode (LED) Packaging Technology "
Walwaikar, Anisha Upendra
Santos, Daryl
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Latin Dissertation
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| Language of Document
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English
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| Record Number
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1052852
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| Doc. No
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TL51969
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| Main Entry
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Walwaikar, Anisha Upendra
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| Title & Author
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Design, Prototyping, and System-Level Analysis of a Novel Light Emitting Diode (LED) Packaging Technology\ Walwaikar, Anisha UpendraSantos, Daryl
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| College
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State University of New York at Binghamton
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| Date
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2019
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| Degree
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Ph.D.
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2019
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| Note
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186 p.
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| Abstract
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This research provides a comprehensive study on the feasibility of the use of Power Overlay (POL) technology for high-power Light Emitting Diode (LED) packages from both a thermal- and reliability perspective. This technology incorporates thermal vias in a low thermal conductivity polyimide substrate directly below the LED chip to reduce the thermal resistance and, thereby, improve the thermal architecture of the LED prototype. The research evaluates the thermal-performance at the package- and system-level prior to fabrication, provides a proof of concept, experimentally measures thermal performance, validates thermal model, performs reliability tests to study its failure mechanisms, and highlights the importance of efficient thermal architecture and the need to choose the right packaging material. The package- and system-level analysis show that the copper vias that extend from the LED die to the package contact pads provide the primary heat dissipation path for the LED package. This is due to the low thermal conductivity of the polyimide and epoxy-based adhesive. The second-level assembly (FR-4 board) adds additional thermal nodes in the heat dissipation path and, therefore, increases the overall temperature and the thermal resistance of the structure. The experimental results obtained using IR Microscopy shows that the inherent chip properties and localized heating not captured in the thermal model leads to asymmetric thermal profiles on the fabricated LED prototype. Therefore, the average chip surface temperature is used to compare and validate the experimental results with the thermal model. Wall-plug efficiency (WPE) is estimated by comparing the average surface temperatures obtained using the thermal model and IR Microscopy. The results indicate that the estimated WPE varies as a function of the input power. The increase in the input power results in a decrease in the WPE and vice versa. A reliability test performed to study the failure analysis shows that the combination of high temperature and high photon flux causes degradation of epoxy-based adhesive in the current design. Therefore, further improvements in the design are required to enhance the functionality and reliability of the LED prototype, especially with respect to choosing the epoxy-based adhesive material that can withstand high temperature and high photon flux.
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| Descriptor
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Design
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Industrial engineering
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Packaging
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Santos, Daryl
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State University of New York at Binghamton
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