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" Architectural Alternatives to Implement High-Performance Delta-Sigma Modulators "
Honarparvar, Mohammad
Sawan, Mohamad
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Latin Dissertation
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English
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| Record Number
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1111923
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TLpq2507276270
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| Main Entry
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Honarparvar, Mohammad
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Sawan, Mohamad
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| Title & Author
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Architectural Alternatives to Implement High-Performance Delta-Sigma Modulators\ Honarparvar, MohammadSawan, Mohamad
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| College
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Ecole Polytechnique, Montreal (Canada)
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| Date
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2019
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| student score
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2019
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| Degree
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Ph.D.
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| Page No
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126
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| Abstract
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The need for hand-held devices, smart-phones and medical implantable microelectronic systems, is remarkably growing up. However, keeping all these electronic devices power optimized is one of the main challenges due to the lack of long life-time batteries utilized to power them up. It is a well-established fact that analog-to-digital converter (ADC) is one of the most critical building blocks of such devices and it needs to efficiently convert analog signals to the digital world to perform post processing such as channelizing, feature extraction, etc. Among various type of ADCs, Delta Sigma Modulators (∆ΣMs) have been widely used in those devices due to the tempting features they offer. In fact, due to oversampling and noise-shaping technique a high-resolution ADC can be achieved with ∆Σ architectures. It also offers a compromise between sampling frequency and resolution while providing a highly programmable approach to realize an ADC. Moreover, such ADCs can be implemented with low-precision analog blocks. Last but not the least, they are capable of being effectively power optimized at both architectural and circuit levels. The latter has been a motivation to proposed different architectures over the years. This thesis contributes to this topic by exploring new architectures to effectively optimize the ∆ΣM structure in terms of resolution, power consumption and chip area. Special cares must also be taken into account to ease the implementation of the ∆ΣM. On the other hand, advanced node CMOS processes bring remarkable improvements in terms of speed, size and power consumption while implementing digital circuits. Such an aggressive process scaling, however, make the design of analog blocks, e.g. operational transconductance amplifiers (OTAs), cumbersome. Therefore, special cares are also taken into account in this thesis to overcome the mentioned issues. Having had above mentioned discussion, this thesis is mainly split in two main categories. First category addresses new architectures implemented in a pure voltage domain and the second category contains new architecture realized in a hybrid voltage and time domain. In doing so, the thesis first focuses on a switched-capacitor implementation of a ∆ΣM while presenting an architectural solution to overcome the limitations of the previous approaches. This limitations include a power hungry adder in a conventional feed-forward topology as well as power hungry OTAs. An inverter-based amplifier is also proposed to realize the integrators of the switched-capacitor ∆ΣM. It is shown that the proposed OTA is robust enough over process, voltage and temperatures (PVTs). For the second part of the thesis, it is demonstrated that a hybrid voltage and time domain is an acceptable venue to implement a ∆ΣM. Therefore, a continuous time gated ring oscillator based MASH ∆ΣM is targeted for the second part of the thesis. It is shown that the power budget of ∆ΣMs is mostly limited by the operational amplifiers required to realize the loop filter. To tackle this issue, part of the design is shifted to the time-domain to take the advantages of a scaling friendly environment. Moreover, the proposed hybrid solution eases the implementation of the ∆ΣM.
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Acoustics
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Artificial intelligence
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Computer science
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Electrical engineering
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Information technology
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