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" Architectures for arithmetic operations in Galois fields GF(2('m)) "


Document Type : Latin Dissertation
Language of Document : English
Record Number : 1112848
Doc. No : TLpq238117855
Main Entry : M. Ahsan
Title & Author : Architectures for arithmetic operations in Galois fields GF(2('m))\ M. Ahsan
College : King Fahd University of Petroleum and Minerals (Saudi Arabia)
Date : 1995
student score : 1995
Degree : M.S.
Page No : 125
Abstract : Galois fields are used in numerous applications like Reed-Solomon (RS) codes, digital signal processing (DSP) and cryptology. There is a need for efficient multiplication and division methods that can be easily realised on VLSI chips. Massey and Omura have recently developed a new multiplication algorithm for Galois fields based on the normal basis representation. A new bit-serial modified Massey-Omura multiplier is developed in this thesis to compute multiplications over GF(2). In contrast to the existing multipliers, this new multiplier requires the minimum chip area. A serial-in serial-out systolic array is presented for performing element inversion with standard basis represented. The architecture is highly regular, modular and nearest neighbor connected. Furthermore, a systolic architecture for an RS encoder, based on Cauchy representation of generator matrix of the code, is presented, consisting of r + 1 cells, where r is the redundancy of the code. This encoder is systematic, does not require any feedback or other global signals. Its cells are of low complexity and it is easily reconfigurable for variable redundancy and changes in the choice of the generator polynomial of the code, the architecture is suitable for very high-speed applications. Finally, a systolic array of an RS decoder, is presented. Systolic array architectures are derived for the various steps including syndrome calculation, key equation solution and error evaluation. The improvements over existing systolic implementations are discussed.
Subject : Applied sciences
: Electrical engineering
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