VLSI test pattern generation under massively observable conditions

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منو

" VLSI test pattern generation under massively observable conditions "
J. M. Boura A. Hubbard

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	1112946
Doc. No	:	TLpq304434441
Main Entry	:	A. Hubbard
	:	J. M. Boura
Title & Author	:	VLSI test pattern generation under massively observable conditions\ J. M. BouraA. Hubbard
College	:	Boston University
Date	:	1998
student score	:	1998
Degree	:	Ph.D.
Page No	:	91
Abstract	:	An algorithm for test generation for combinatorial VLSI circuits under massively observable conditions is developed. The algorithm provides a means of determining single and multiple test sets that can be used for circuit verification under the single stuck-at fault model. The algorithm is based on analyzing the logical functionality of each node in the circuit. The new methodology differs substantially from all current approaches. Current techniques execute a topological search algorithm to control internal nodes and propagate their state to an output pin. Our technique transforms the test-generation problem into a logic minimization process by defining a logic function on the set of covering cubes. Theoretical estimates on the average time cost of the algorithm are developed. The average time cost of the conventional method is a cubic function of the number of nodes (i.e. usd\rm O(Z\sp3)).usd With the new methodology, the cost becomes usd\rm O(ZL\sp2),usd where L is the average number of cubes per node. Moreover, producing other possibly shorter test sets requires that the procedure of the conventional methodology be repeated at a cost of usd\rm O(Z\sp3).usd With the new algorithm, additional test sets are obtained at an additional computational cost that is O(Ln(L)). An implementation of the algorithm is realized using C++. Twenty example circuits are used to compare test generation times and test sets produced by SIS against the new algorithm. To make the comparison equitable, all internal nodes were specified as observable to SIS. The new algorithm's run times are better than SIS in 85% of the cases and the average speed up is 51.9%. Test lengths are reduced from 14% to 97%, and the average test length reduction is 81%. ftnSIS is a public domain synthesis and test generation system from UC Berkeley.
Subject	:	Applied sciences
	:	Electrical engineering
	:	topological search
	:	verification