A parallel binary structured LMS algorithm for transversal adaptive filters

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" A parallel binary structured LMS algorithm for transversal adaptive filters "
M. Eshghi J. DeGroat

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	1113028
Doc. No	:	TLpq304115018
Main Entry	:	J. DeGroat
	:	M. Eshghi
Title & Author	:	A parallel binary structured LMS algorithm for transversal adaptive filters\ M. EshghiJ. DeGroat
College	:	The Ohio State University
Date	:	1994
student score	:	1994
Degree	:	Ph.D.
Page No	:	159
Abstract	:	The adaptation process in digital filters requires extensive calculation. This computation makes adaptation a slow and time consuming process. Simple, but versatile, parallel algorithms for adaptive filters, suitable for VLSI implementation, are in demand. In this dissertation a regular and modular parallel algorithm for an adaptive filter is presented. This parallel structure is based on the Gradient Vector Estimation Algorithm, which minimizes the Mean Square Error. In the parallel method, the tap weights of the adaptive filter are updated every s steps, whereas in the recursive algorithms, the tap weights are updated at each step. For s step update, bit strings of length s are used to derive the terms with which the tap weights of the adaptive filter are calculated. The presented parallel algorithm computes the tap weights at time n + s as a function of the tap weights at time n, the inputs from time n + 1 to n + s 1, and the desired output from time n + 1 to n + s 1. The algorithm can be mapped to a VLSI architecture that is both regular and modular and allows either expansion of the order of the filter or the degree of parallelism obtainable. A comparison between the performance of the parallel LMS algorithm, Fast Exact LMS algorithm, and the parallel binary structured LMS algorithm is presented. Based on the proposed algorithm and employing the maximum pipelining, a VHDL model for an adaptive filter is developed. This model verifies the functional behavior of the algorithm as implemented in hardware. The model also simulates the timing of the circuit. This simulation shows the highly regular and modular structure of the algorithm. It is also a practical evidence that the proposed algorithm is suitable for a VLSI implementaton.
Subject	:	Applied sciences
	:	Electrical engineering