Design, modeling, and VLSI implementation of a RISC dataflow array processor

مرکز و کتابخانه مطالعات اسلامی به زبان های اروپایی

منو

" Design, modeling, and VLSI implementation of a RISC dataflow array processor "
A. A. Farooqui

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	1113033
Doc. No	:	TLpq231603837
Main Entry	:	A. A. Farooqui
Title & Author	:	Design, modeling, and VLSI implementation of a RISC dataflow array processor\ A. A. Farooqui
College	:	King Fahd University of Petroleum and Minerals (Saudi Arabia)
Date	:	1995
student score	:	1995
Degree	:	M.S.
Page No	:	132
Abstract	:	In this thesis the design and VLSI implementation of a highly reconfigurable Dataflow RISC Array processor (DF-RISC-A) is presented. This array processor possesses all the features of static and dynamic dataflow models. It can execute arbitrary algorithms (both recursive and regular), in static and dynamic manner. In order to increase the speed and reduce VLSI chip area, a RISC methodology has been adopted. Each processing element can execute 25-instructions. In order to facilitate maximum communication between PEs, each PE can communicate with its 8 immediate neighbors using the boundary registers/ports, while it can communicate with the non-neighbor PEs and the host using the communication network and the host bus which runs between two alternate rows of PEs. This results in tighter coupling and faster communication among processing elements. Since the topology can be reconfigurable, it is possible to implement any dataflow graph on this processor array. A 'Global Network Controller' takes care of the communication between PEs and host. It generates control signals for data transfer between host and PE. A PE can communicate with the host only through this communication controller. This network controller is used to interface the processor array with the parallel port of a Personal Computer. The processor has been modeled at behavioral level in VHDL, and gate level implementation has been done using OASIS Logic3 Silicon compiler. Each processing element requires 4261 CMOS gates with an area of 7512 x 8081 mum2.
Subject	:	Applied sciences
	:	Computer science
	:	Electrical engineering
	:	Electrical engineering