Design of phase-locked loop (PLL) for ghost cancellation chip using CMOS technology

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" Design of phase-locked loop (PLL) for ghost cancellation chip using CMOS technology "
K. S. Islam J. S. Linder

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	1113130
Doc. No	:	TLpq304415004
Main Entry	:	J. S. Linder
	:	K. S. Islam
Title & Author	:	Design of phase-locked loop (PLL) for ghost cancellation chip using CMOS technology\ K. S. IslamJ. S. Linder
College	:	Texas A&M University - Kingsville
Date	:	1997
student score	:	1997
Degree	:	M.S.
Page No	:	95
Abstract	:	The main objective of this thesis is to design a fully integrated charge pump PLL for application and integration on a high-frequency ghost cancellation chip. Since microprocessor operate at very high clock frequency, it becomes necessary to eliminate the delay between external and internal clocks (clock skew). This thesis will deal with the design of a charge pump phase-locked loop as a part of a high-performance ghost cancellation chip set. A charge-pump phase-locked loop (CPPLL) calibrates the delay per stage of the delay line. Using this technique, it is possible to obtain an accurate phase relationship between an off-chip reference clock and the internal clock signals. This CPPLL will be fully integrated onto a ghost cancellation chip in 2.0-um CMOS technology without the need for external components. (1,2) ftnThis thesis has been partially supported by the NASA grants NAG-5-929 and NAG-9-333.
Subject	:	Applied sciences
	:	Electrical engineering