Fabrication and characterization of sub-0.25 micrometer CMOS p-n junctions by low energy gallium ion...

مرکز و کتابخانه مطالعات اسلامی به زبان های اروپایی

منو

" Fabrication and characterization of sub-0.25 micrometer CMOS p-n junctions by low energy gallium ion focused ion beam implantation "
H. C. Mogul A. J. Steckl

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	1113270
Doc. No	:	TLpq304112650
Main Entry	:	A. J. Steckl
	:	H. C. Mogul
Title & Author	:	Fabrication and characterization of sub-0.25 micrometer CMOS p-n junctions by low energy gallium ion focused ion beam implantation\ H. C. MogulA. J. Steckl
College	:	University of Cincinnati
Date	:	1994
student score	:	1994
Degree	:	Ph.D.
Page No	:	212
Abstract	:	The main thrust of this thesis is the investigation of a Focused Ion Beam (FIB)-based approach for fabricating p-n shallow junctions approaching the nanometer scale (15-50 nm) which will be compatible with future generation CMOS technology. Ultra shallow junctions are formed by directly implanting low energy (3-25 keV) Ga ions into a crystalline Si substrate using a FIB implanter. Secondary ion mass spectrometry (SIMS) was employed as an analytical tool to measure the depth distribution of low energy Ga ions between 2keV to 10keV implanted into crystalline Si. The issue of ion channeling was investigated by implanting low-energy off-axis Ga ions at various tilt angles. The Ga atomic depth profile was measured using SIMS and the fractions of the Ga dose found in the tail of distribution when compared to a pure Gaussian profile for the 5keV implant were usd\approxusd16% and 10% for the 0 and 15 off-axis implantation, respectively. Cross-sectional TEM was used to characterize the resulting structure of the implanted layer. For 5keV Ga implantation, the xTEM measurement yielded an amorphous layer thickness of 9 nm and a line of end-of-range defects 16nm below the surface (after RTA). SRP measurements were performed to characterize the junction depths and to obtain the activated Ga depth profile. At 4keV an electrical junction depth of 15nm is obtained from spreading resistance profiling (SRP). Effects of rapid thermal annealing on sub-100nm p-n Si junctions fabricated using 10keV FIB Ga implantation at doses ranging from 10 to 10cm were reported. Electrical properties of the diodes fabricated on n-Si with Nb = (5-10) usd\timesusd 10 by on-axis Ga FIB implantation at 4 to 25keV were obtained from I-V characteristics. p-n junction diodes for sub0.25mum CMOS circuits were fabricated using FIB Ga implantation into n-Si Nb = (1-10) usd\timesusd 10cm. Implant energy was varied from 2 to 50keV at doses ranging 1 usd\timesusd 10 to 1 usd\timesusd 10cm with different scan speeds. FIB Ga implantation through Ti metal (ITM) and TiSi2 (ITS) layers, followed by rapid thermal annealing (RTA) has been investigated for application in self-aligned silicide technology. Electrochemical capacitance-voltage (ECV) profiling technique was employed to measure the active carrier concentration in nanoscale layers fabricated by focused ion beam (FIB) implantation of 3 to 10keV Ga ions into crystalline Si. (Abstract shortened by UMI.)
Subject	:	@p n junction
	:	Applied sciences
	:	Condensation
	:	Electrical engineering
	:	gallium
	:	Pure sciences