Design of an SRAM with on-chip error detection and correction for single event upset immunity

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" Design of an SRAM with on-chip error detection and correction for single event upset immunity "
N. Mohammad J. S. Linder

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	1113277
Doc. No	:	TLpq304443165
Main Entry	:	J. S. Linder
	:	N. Mohammad
Title & Author	:	Design of an SRAM with on-chip error detection and correction for single event upset immunity\ N. MohammadJ. S. Linder
College	:	Texas A&M University - Kingsville
Date	:	1997
student score	:	1997
Degree	:	M.S.
Page No	:	125
Abstract	:	An architectural design of a Static RAM with on-chip error detection and correction is developed. A correcting code called Linear Block Code is implemented for Single Error Correction and Double Error Detection (SEC-DED). A special arrangement of the codewords is used to minimize the possibility of double error in a single codeword. A special address generation technique is implemented to arrange codewords on the SRAMs and also to read codewords out of the SRAMs. The architecture is designed in such a way that the external Read/Write operation has priority over error detection and correction processes. A Hardware Description Language (VHDL) is used for this design. Synopsis synthesis is used to extract gate level netlist of the design from the VHDL code. ftnThis thesis work is partially supported by NASA grants NAG-5929 and NAG-9-333.
Subject	:	Applied sciences
	:	Electrical engineering