NASICs: A 'fabric-centric' approach towards integrated nanosystems

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" NASICs: A 'fabric-centric' approach towards integrated nanosystems "
Pritish Narayanan C. A. Moritz

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	41044
Doc. No	:	TL14488
Call number	:	‭3556273‬
Main Entry	:	Pritish Narayanan
Title & Author	:	NASICs: A 'fabric-centric' approach towards integrated nanosystems\ Pritish NarayananC. A. Moritz
College	:	University of Massachusetts Amherst
Date	:	2013
Degree	:	Ph.D.
student score	:	2013
Page No	:	126
Abstract	:	This dissertation addresses the fundamental problem of how to build computing systems for the nanoscale. With CMOS reaching fundamental limits, emerging nanomaterials such as semiconductor nanowires, carbon nanotubes, graphene etc. have been proposed as promising alternatives. However, nanoelectronics research has largely focused on a 'device-first' mindset without adequately addressing system-level capabilities, challenges for integration and scalable assembly. In this dissertation, we propose to develop an integrated nano-fabric, (broadly defined as nanostructures/devices in conjunction with paradigms for assembly, interconnection and circuit styles), as opposed to approaches that focus on MOSFET replacement devices as the ultimate goal. In the 'fabric-centric' mindset, design choices at individual levels are made compatible with the fabric as a whole and minimize challenges for nanomanufacturing while achieving system-level benefits vs. scaled CMOS. We present semiconductor nanowire based nano-fabrics incorporating these fabric-centric principles called NASICs and N3ASICs and discuss how we have taken them from initial design to experimental prototype. Manufacturing challenges are mitigated through careful design choices at multiple levels of abstraction. Regular fabrics with limited customization mitigate overlay alignment requirements. Cross-nanowire FET devices and interconnect are assembled together as part of the uniform regular fabric without the need for arbitrary fine-grain interconnection at the nanoscale, routing or device sizing. Unconventional circuit styles are devised that are compatible with regular fabric layouts and eliminate the requirement for using complementary devices. Core fabric concepts are introduced and validated. Detailed analyses on device-circuit co-design and optimization, cascading, noise and parameter variation are presented. Benchmarking of nanowire processor designs vs. equivalent scaled 16nm CMOS shows up to 22X area, 30X power benefits at comparable performance, and with overlay precision that is achievable with present-day technology. Building on the extensive manufacturing-friendly fabric framework, we present recent experimental efforts and key milestones that have been attained towards realizing a proof-of-concept prototype at dimensions of 30nm and below.
Subject	:	Applied sciences; Emerging technology; Nano-fabric; Nanoscale manufacturing; Nasics; Post-cmos computing systems; Semiconductor nanowires; Computer Engineering; Electrical engineering; Nanotechnology; 0464:Computer Engineering; 0544:Electrical engineering; 0652:Nanotechnology
Added Entry	:	C. A. Moritz
Added Entry	:	University of Massachusetts Amherst