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Aggressive scaling of Silicon CMOS feature size has led to increased integration density and improved system performance. However, when scaling approaches its fundamental limit, it is extremely difficult to carry it further along Moore's law curve. To meet the continuously increased demand for performance, there is a need for non-CMOS based heterogenous systems that can add special functions to standard CMOS which are either cheap or not easily implementable in Silicon CMOS. However, designing such complex systems with various technologies poses a set of new challenges in terms of design, test, fabrication and integration. To address those challenges, in this research, we develop an alternate technology-aware system design methodology, which takes the best of different technologies and provides efficient solutions considering different levels of design abstraction, namely, device, circuit and micro-architecture. To demonstrate the feasibility of proposed design concept, in this research, we explore two emerging technologies--flexible electronics and spintronics. Specifically, for the first time, we extend the application space of flexible electronics to high performance and low power domain. In particular, we develop a generic and reconfigurable test engine using low temperature polycrystalline Silicon thin film transistor (LTPS TFT) to improve the reliability and verification of complex VLSI system. Efficient computer-aided design (CAD) tools are also developed for circuit simulation and yield estimation. Based on the tools, statistical circuit design methodology is proposed to address the design challenges introduced by inherent material variations. In addition, we explore the application of spintronics as embedded memory for future computer architecture. The immature fabrication-process-induced variation significantly affects the stability of Spin Torque Transfer Magnetic Random Access Memory (STT-MRAM) and degrades the yield. To address the challenges, we develop analysis/estimation methods of parametric failures, explore circuit/architecture optimization possibilities for better cell stability, and high density without incurring expensive technology modification.
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