Novel low power CAM architecture

مرکز و کتابخانه مطالعات اسلامی به زبان های اروپایی

منو

" Novel low power CAM architecture "
Ka Fai Ng K. Hsu

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	53367
Doc. No	:	TL23321
Call number	:	‭1456794‬
Main Entry	:	Ka Fai Ng
Title & Author	:	Novel low power CAM architecture\ Ka Fai Ng
College	:	Rochester Institute of Technology
Date	:	2008
Degree	:	M.S.
student score	:	2008
Page No	:	88
Abstract	:	One special type of memory use for high speed address lookup in router or cache address lookup in a processor is Content Addressable Memory (CAM). CAM can also be used in pattern recognition applications where a unique pattern needs to be determined if a match is found. CAM has an additional comparison circuit in each memory bit compared to Static Random Access Memory. This comparison circuit provides CAM with an additional capability for searching the entire memory in one clock cycle. With its hardware parallel comparison architecture, it makes CAM an ideal candidate for any high speed data lookup or for address processing applications. Because of its high power demand nature, CAM is not often used in a mobile device. To take advantage of CAM on portable devices, it is necessary to reduce its power consumption. It is for this reason that much research has been conducted on investigating different methods and techniques for reducing the overall power. The objective is to incorporate and utilize circuit and power reduction techniques in a new architecture to further reduce CAM's energy consumption. The new CAM architecture illustrates the reduction of both dynamic and static power dissipation at 65nm sub-micron environment. This thesis will present a novel CAM architecture, which will reduce power consumption significantly compared to traditional CAM architecture, with minimal or no performance losses. Comparisons with other previously proposed architectures will be presented when implementing these designs under 65nm process environment. Results show the novel CAM architecture only consumes 4.021mW of power compared to the traditional CAM architecture of 12.538mW at 800MHz frequency and is more energy efficient over all other previously proposed designs.
Subject	:	Applied sciences; CAM; Content addressable memory; Low power; Memory; Electrical engineering; 0544:Electrical engineering
Added Entry	:	K. Hsu
Added Entry	:	Rochester Institute of Technology