Hardware/software optimizations for elliptic curve scalar multiplication on hybrid FPGAs

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" Hardware/software optimizations for elliptic curve scalar multiplication on hybrid FPGAs "
Glenn Ramsey, Jr. M. Lukowiak

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	54002
Doc. No	:	TL23956
Call number	:	‭1457505‬
Main Entry	:	Glenn Ramsey, Jr.
Title & Author	:	Hardware/software optimizations for elliptic curve scalar multiplication on hybrid FPGAs\ Glenn Ramsey, Jr.
College	:	Rochester Institute of Technology
Date	:	2008
Degree	:	M.S.
student score	:	2008
Page No	:	146
Abstract	:	Elliptic curve cryptography (ECC) offers a viable alternative to Rivest-Shamir-Adleman (RSA) by delivering equivalent security with a smaller key size. This has several advantages, including smaller bandwidth demands, faster key exchange, and lower latency encryption and decryption. The fundamental operation for ECC is scalar point multiplication, wherein a point P on an elliptic curve defined over a finite field is multiplied by a scalar k. The complexity of this operation requires a hardware implementation to achieve high performance. The algorithms involved in scalar point multiplication are constantly evolving, incorporating the latest developments in number theory to improve computation time. These competing needs, high performance and flexibility, have caused previous implementations to either limit their adaptability or to incur performance losses. This thesis explores the use of a hybrid-FPGA for scalar point multiplication. A hybrid-FPGA contains a general purpose processor (GPP) in addition to reconfigurable fabric. This allows for a software/hardware co-design with low latency communication between the GPP and custom hardware. The elliptic curve operations and finite field inversion are programmed in C code. All other finite field arithmetic is implemented in the FPGA hardware, providing higher performance while retaining flexibility. The resulting implementation achieves speedups ranging from 24 times to 55 times faster than an optimized software implementation executing on a Pentium II workstation. The scalability of the design is investigated in two directions: faster finite field multiplication and increased instruction level parallelism exploitation. Increasing the number of parallel arithmetic units beyond two is shown to be less efficient than increasing the speed of the finite field multiplier.
Subject	:	Applied sciences; Cryptography; Elliptic curve; FPAGs; Finite field; VHDL; Electrical engineering; 0544:Electrical engineering
Added Entry	:	M. Lukowiak
Added Entry	:	Rochester Institute of Technology