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Document Type:Latin Dissertation
Language of Document:English
Record Number:54085
Doc. No:TL24039
Call number:‭3282814‬
Main Entry:Mohammad Reshadi
Title & Author:No -instruction -set -computer (NISC) technology modeling and compilationMohammad Reshadi
College:University of California, Irvine
Date:2007
Degree:Ph.D.
student score:2007
Page No:135
Abstract:Due to the productivity gain of using software in the design of embedded systems, processors are increasingly used in these systems. Embedded processors often run only one or a few applications in the life-time of the system. Therefore, they can be customized for the target applications and significantly improve the quality of the embedded system in terms of cost or other constraints such as performance, and power consumption. Instruction-based architectures limit the customizations because: (a) hardware designer is limited by instruction coding, size and complexity of the decoder; (b) compilers can support certain class of instructions and hence instructions cannot be very complex; and (c) manually updating compilers to incorporate the custom instructions is not practical and developing compilers that automatically utilize hardware customizations through new custom instructions is very complex. On the other hand using technologies such as High Level Synthesis (HLS) is not always possible because the traditional HLS techniques can only support relatively small applications. Also they do not give enough control to the designer over the quality of results. Additionally, the main interdependent subtasks of HLS, i.e. resource allocation, operation scheduling, and resource binding, are already too complex themselves and hence adding new constrains such as design for manufacturability to them is not practical. In this thesis we present a new design approach called NISC (No-Instruction-Set-Computer) Technology. In NISC, the datapath and controller are generated in two different phases. First the datapath is generated or selected from a database based on the application behavior. At the core of NISC technology, there is a cycle-accurate compiler that maps a given application directly on a given datapath and generates the control words (CWs) that control the datapath resources in every clock cycle. The NISC architecture style is similar to the old nanocode machines. However, instead of using nanocodes inside the process for implementing the microcodes and in turn instructions, in NISC the nanocode (CWs) are directly used to program the datapath. NISC simplifies customization and allows designer to fully control design quality. NISC simplifies ASIP (Application-Specific-Instruction-Processor) approach by removing the complex task of finding and designing "most profitable" custom instructions. In NISC only the datapath needs to be specified and NISC compiler generates code as if each basic block of the program is executed with one custom instruction. On the other hand, NISC improves resource constrained HLS techniques by adding the connectivity constraints, on top of the traditional resource constraints, into synthesis process. This enables the designer to control every thing in datapath including wires, which are becoming increasingly more critical in newer technologies. To realize the NISC Technology design flow, several challenging categories of problems must be solved. Mainly we need: (1) Techniques for efficiently designing and customizing a datapath for an application (2) Techniques for efficiently compiling any application on any given datapath (3) Techniques for efficiently synthesizing a controller from the output of compiler and then generating synthesizable code for different target implementations. In this thesis we focus on the compilation problems to enable practical use of NISC IPs in a system. We mainly address: modeling of datapath for compilation, scheduling algorithm for compilation, interrupt support in the statically-scheduled pipelined NISC components, and low-level programming in C language in the absence of assembly. Finally we show how different communication interfaces and protocols can be added and used in a NISC component. At the end, we present results that show efficient and fast compiler as well as significant quality improvements for presented experiments. A working compiler incorporating all of the solutions in this thesis, along with the experiments and other NISC toolsets is vailable for public use from NISC website http://www.cecs.uci.edu/-nisc/ . An online version of the tools can be also directly accessed at this website.
Subject:Applied sciences; Compilation; Hardware; High-level synthesis; NISC; No-instruction-set-computer; Processors; Scheduling algorithms; Computer science; 0984:Computer science
Added Entry:D. Gajski
Added Entry:University of California, Irvine