Study of hardware and software optimizations of SPEA2 on hybrid FPGAs

مرکز و کتابخانه مطالعات اسلامی به زبان های اروپایی

منو

" Study of hardware and software optimizations of SPEA2 on hybrid FPGAs "
Brad Theophila M. Lukowiak

Document Type	:	Latin Dissertation
Language of Document	:	English
Record Number	:	55142
Doc. No	:	TL25096
Call number	:	‭1454539‬
Main Entry	:	Brad Theophila
Title & Author	:	Study of hardware and software optimizations of SPEA2 on hybrid FPGAs\ Brad Theophila
College	:	Rochester Institute of Technology
Date	:	2008
Degree	:	M.S.
student score	:	2008
Page No	:	90
Abstract	:	Traditional radar technology consists of multiple platforms, each designed to process only a single mission objective, such as Ground Moving Target Indication (GMTI), Airborne Moving Target Indication (AMTI) or Synthetic Aperture Radar (SAR). This is no longer considered a cost effective solution, thus leading to the increased need for a single radar platform which can perform multiple radar missions. Many algorithms have been developed to specifically address multi-objective design problems. One such approach, the Strength Pareto Evolutionary Algorithm 2 (SPEA2), applies the concept of evolution through a Genetic Algorithm (GA) to the design of simultaneous orthogonal waveforms. The objectives of the various radar missions are often conflicting. The goal of SPEA2 is to find the best waveform suite in the Pareto sense. Preliminary results of this algorithm applied to a scaled down multi-objective mission scenario have been promising. One setback of the use of this algorithm is its abundant computational complexity. Even in a scaled down simulation, performance does not meet expectations. This thesis investigated a hardware and software optimization of SPEA2 applied to simultaneous multi-mission waveform design, using hybrid FPGAs. Hybrid FPGAs contain a combination of a single or multiple embedded processors and reconfigurable hardware. The algorithm was first implemented in C on a PC, then profiled and analyzed. The C code was translated to run on an embedded PowerPC 405 processing core on a Virtex4 FX (V4FX). The hardware fabric of the V4FX was utilized to offload the main bottleneck of the algorithm from the PowerPC 405 core to hardware for speedup, while various software optimizations were also implemented, in an effort to improve performance. Performance results from the V4FX implementation were not ideal. Thus, many suggestions for future work that may achieve the desired performance are posed in this thesis.
Subject	:	Applied sciences; Genetic algorithm; Hybrid FPGA; Multimission radar waveform; Multiobjective optimization; Electrical engineering; Artificial intelligence; Computer science; 0984:Computer science; 0544:Electrical engineering; 0800:Artificial intelligence
Added Entry	:	M. Lukowiak
Added Entry	:	Rochester Institute of Technology