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Document Type:Latin Dissertation
Language of Document:English
Record Number:55379
Doc. No:TL25333
Call number:‭3403420‬
Main Entry:Dhanoop Varghese
Title & Author:Multi-probe experimental and 'bottom-up' computational analysis of correlated defect generation in modern nanoscale transistorsDhanoop Varghese
College:Purdue University
Date:2009
Degree:Ph.D.
student score:2009
Page No:187
Abstract:As transistors are getting smaller, it has become increasingly difficult to achieve requisite device performance for new generations of ICs. Two approaches are being considered: Replacing Si-SiO2 transistors with higher performance III-V transistors, or operating the classical transistors close to their reliability limits. In the first part of the thesis, we consider the problem of interface defects with various combinations of gate oxides and substrate materials. We use a combination of characterization techniques to profile the interface and bulk defects in both position and energy, and also to understand how the defect charge level changes with its occupation probability. This multi-probe analysis is necessary to differentiate between the acceptorand donor-like defects and to obtain an accurate estimate of the defect densities. We show that the nature of the defect (acceptor-like vs. donor-like) at In 0.65 Ga0.35 As/Al2 O3 interface plays a significant role in determining whether surface inversion is possible for these novel transistor structures. In the second part, we consider the problem of reliability close to the physical limit where classical perspectives must be supplemented by 'bottom-up' considerations. The reliability studies are traditionally carried out as stand-alone analysis at specific operating bias conditions like NBTI, HCI, and TDDB. The defect generation at various bias conditions however depends on parameters like carrier densities, process conditions, material properties etc., and therefore should be a part of the reliability analysis. As a specific example to the general "bottom-up" approach we propose, we study the non-classical OFF-state degradation in Drain Extended MOS (DeMOS) transistors. These transistors show correlated parameter degradation and dielectric breakdown when biased in OFF-state conditions (V G =0V, |VD |>5V) and as such defy classical reliability classification. We show that the OFF-state degradation in DeMOS transistors is due to interfacial ≡Si"YO bonds broken by hot carriers generated from band-to-band tunneling followed by impact ionization. The resultant degradation exhibits a unique scaling law, which enables accurate lifetime extrapolation based on short term measurements. The saturating nature of the degradation curve is explained based on bond-dispersion (B-D) model, which assigns a finite spread to the ≡Si--O bond energy within the amorphous SiO 2 . OFF-state TDDB is shown to be due to ≡Si--O bonds broken in the bulk of the oxide by exactly identical mechanism, and is therefore shown to correlate with interface damage. The breakdown statistics of the OFF-state TDDB is consistently explained based on asymmetric percolation model. The generalized approach thus explains the correlated degradation in DeMOS transistors and significantly reduces the characterization time and cost. The above framework to analyze non-classical OFF-state degradation is however general and is not limited to a specific operating condition or device structure. We therefore analyzed ON-state hot carrier degradation in DeMOS transistors based on the "bottom-up" approach and verified that the basic degradation mechanism and features of OFF-state degradation remain invariant in spite of the orders of magnitude increase in drain current. We also studied ON-state degradation in logic transistors from various technology nodes, and remarkably the universality of hot carrier degradation is shown to be valid even for the ultra-scaled transistors operating at much lower operating biases. Classical hot carrier models cannot be used to analyze hot carrier degradation in these ultra-scaled transistors as the substrate current is contaminated by excessive gate leakage. Instead, we demonstrate how the universality of hot carrier degradation can be used to perform fast and accurate hot carrier lifetime extrapolation based on short-term measurements. Our multi-probe experimental and "bottom-up" computational approach thus provides new insights into the defect generation at oxide/substrate interface and provides a model independent methodology for hot carrier lifetime extrapolation.
Subject:Applied sciences; Defects; Nanoscale transistors; Bond-dispersion model; Gate dielectric breakdown; Hot carrier degradation; III-V MOSFET; Percolation model; Universal degradation; Electrical engineering; 0544:Electrical engineering
Added Entry:M. A. Alam
Added Entry:Purdue University