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" SystemVerilog For Design "
by Stuart Sutherland, Simon Davidmann, Peter Flake.
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BL
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574654
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b403873
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Sutherland, Stuart.
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| Title & Author
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SystemVerilog For Design : A Guide to Using SystemVerilog for Hardware Design and Modeling /\ by Stuart Sutherland, Simon Davidmann, Peter Flake.
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| Publication Statement
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Boston, MA :: Springer US :: Imprint: Springer,, 2004.
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| ISBN
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9781475766820
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: 9781475766844
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| Contents
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1: Introduction to SystemVerilog -- 2: SystemVerilog Literal Values and Built-in Data Types -- 3: SystemVerilog User-Defined and Enumerated Data Types -- 4: SystemVerilog Arrays, Structures and Unions -- 5: SystemVerilog Procedural Blocks, Tasks and Functions -- 6: SystemVerilog Procedural Statements -- 7: Modeling Finite State Machines with SystemVerilog -- 8: SystemVerilog Design Hierarchy -- 9: SystemVerilog Interfaces -- 10: A Complete Design Modeled with SystemVerilog -- 11: Behavioral and Transaction Level Modeling -- Appendix A: The SystemVerilog Formal Definition (BNF) -- Appendix B: A History of SUPERLOG, The Beginning of SystemVerilog.
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| Abstract
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SystemVerilog is a rich set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language (Verilog HDL). These extensions address two major aspects of HDL based design. First, modeling very large designs with concise, accurate, and intuitive code. Second, writing high-level test programs to efficiently and effectively verify these large designs. This book, SystemVerilog for Design, addresses the first aspect of the SystemVerilog extensions to Verilog. Important modeling features are presented, such as two-state data types, enumerated types, user-defined types, structures, unions, and interfaces. Emphasis is placed on the proper usage of these enhancements for simulation and synthesis. A companion to this book, SystemVerilog for Verification, covers the second aspect of SystemVerilog.
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Engineering.
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Computer-aided design.
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Computer engineering.
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Systems engineering.
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Davidmann, Simon.
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Flake, Peter.
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SpringerLink (Online service)
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