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" Electromigration modeling at circuit layout level "
Cher Ming Tan, Feifei He
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BL
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| Record Number
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595093
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| Doc. No
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b424312
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| Main Entry
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Tan, Cher Ming,1959-
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| Title & Author
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Electromigration modeling at circuit layout level\ Cher Ming Tan, Feifei He
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| Publication Statement
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Singapore ;New York :: Springer,, c2013
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| Series Statement
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SpringerBriefs in applied sciences and technology, Reliability,
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| Page. NO
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1 online resource
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| ISBN
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9789814451215 (electronic bk.)
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: 9814451215 (electronic bk.)
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9789814451208
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Includes bibliographical references
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| Abstract
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Integrated circuit (IC) reliability is of increasing concern in present-day IC technology where the interconnect failures significantly increases the failure rate for ICs with decreasing interconnect dimension and increasing number of interconnect levels. Electromigration (EM) of interconnects has now become the dominant failure mechanism that determines the circuit reliability. This brief addresses the readers to the necessity of 3D real circuit modelling in order to evaluate the EM of interconnect system in ICs, and how they can create such models for their own applications. A 3-dimensional (3D) electro-thermo-structural model as opposed to the conventional current density based 2-dimensional (2D) models is presented at circuit-layout level
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| Subject
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Electrodiffusion-- Simulation methods
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Integrated circuits-- Reliability
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| Dewey Classification
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621.3815
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| LC Classification
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TK7874.T36 2013
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TK7874.T36 2013
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| Added Entry
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He, Feifei
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| Added Entry
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Ohio Library and Information Network
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