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" Design and test technology for dependable systems-on-chip "
Raimund Ubar, Jaan Raik, and Heinrich Theodor Vierhaus, editors.
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BL
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615460
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dltt
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| Title & Author
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Design and test technology for dependable systems-on-chip\ Raimund Ubar, Jaan Raik, and Heinrich Theodor Vierhaus, editors.
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| Publication Statement
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Hershey, Pa. :: IGI Global (701 E. Chocolate Avenue, Hershey, Pennsylvania, 17033, USA),, c2011.
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electronic texts (1 v.) :: digital files.
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| ISBN
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9781609602147
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9781609602123
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1609602129
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Includes bibliographical references.
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| Contents
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1. System-level design of NoC-based dependable embedded systems / Mihkel Tagel, Peeter Ellervee, Gert Jervan -- 2. Synthesis of flexible fault-tolerant schedules for embedded systems with soft and hard timing constraints / Viacheslav Izosimov ... et al. -- 3. Optimizing fault tolerance for multi-processor system-on-chip / Dimitar Nikolov ... et al. -- 4. Diagnostic modeling of digital systems with multi-level decision diagrams / Raimund Ubar ... et al. -- 5. Enhanced formal verification flow for circuits integrating debugging and coverage analysis / Daniel Grosse, Görschwin Fey, Rolf Drechsler -- 6. Advanced technologies for transient faults detection and compensation / Matteo Reorda, Luca Sterpone, Massimo Violante -- 7. Memory testing and self-repair / Mária Fischerová, Elena Gramatová -- 8. Fault-tolerant and fail-safe design based on reconfiguration / Hana Kubatova, Pavel Kubalik -- 9. Self-repair technology for global interconnects on SoCs / Daniel Scheit, Heinrich Vierhaus -- 10. Built-in self repair for logic structures / Tobias Koal, Heinrich Vierhaus --
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11. Self-repair by program reconfiguration in VLIW processor architectures / Mario Schölzel, Pawel Pawlowski, Adam Dabrowski -- 12. Fault simulation and fault injection technology based on SystemC / Silvio Misera, Roberto Urban -- 13. High-level decision diagram simulation for diagnosis and soft-error analysis / Jaan Raik ... et al. -- 14. High-speed logic level fault simulation / Raimund Ubar, Sergei Devadze -- 15. Software-based self-test of embedded microprocessors / Paolo Bernardi ... et al. -- 16. SoC self test based on a test-processor / Tobial Koal, Rene Kothe, Heinrich Vierhaus -- 17. Delay faults testing / Marcel Baláž, Roland Dobai, Elena Gramatová -- 18. Low power testing / Zdenek Kotásek, Jaroslav Škarvada -- 19. Thermal-aware SoC test scheduling / Zhiyuan He, Zebo Peng, Petru Eles -- 20. Study on combined test-data compression and test planning for testing of modular SoCs / Anders Larsson ... et al. -- 21. Reduction of the transferred test data amount / Ondrej Novák -- 22. Sequential test set compaction in LFSR reseeding / Artur Jutman, Igor Aleksejev, Jaan Raik.
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| Abstract
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Covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC).
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Systems on a chip-- Design and construction.
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Networks on a chip-- Design and construction.
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Systems on a chip-- Testing.
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Networks on a chip-- Testing.
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Ubar, Raimund,1941-
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Raik, Jaan,1972-
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Vierhaus, Heinrich Theodor,1951-
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IGI Global.
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