Formal verification :

" Formal verification : "
Erik Seligman, Tom Schubert, M.V. Achutha Kiran Kumar

Document Type	:	BL
Record Number	:	622613
Doc. No	:	dltt
Main Entry	:	Seligman, Erik
Title & Author	:	Formal verification : : an essential toolkit for modern VLSI design /\ Erik Seligman, Tom Schubert, M.V. Achutha Kiran Kumar
Page. NO	:	1 online resource (1 volume) :: illustrations
ISBN	:	9780128008157
	:	: 0128008156
	:	9780128007273
Bibliographies/Indexes	:	Includes bibliographical references and index
Subject	:	Electronic circuits-- Testing
Subject	:	Integrated circuits-- Very large scale integration-- Design and construction
Subject	:	Verilog (Computer hardware description language)
LC Classification	:	‭TK7867‬
Added Entry	:	Schubert, E. Thomas,1959-
	:	Kumar, M V Achutha Kiran
Added Entry	:	Ohio Library and Information Network
Parallel Title	:	Essential toolkit for modern VLSI design
	:	: Essential toolkit for modern very-large scale integration design

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