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" Retargetable processor system integration into multi-processor system-on-chip platforms "
Andreas Wieferink, Heinrich Meyr, Rainer Leupers
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BL
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| Record Number
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697437
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b519626
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| Main Entry
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Wieferink, Andreas
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| Title & Author
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Retargetable processor system integration into multi-processor system-on-chip platforms\ Andreas Wieferink, Heinrich Meyr, Rainer Leupers
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| Publication Statement
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[Dordrecht] :: Springer,, c2008
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| Page. NO
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1 online resource (xvi, 162 p.) :: ill
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| ISBN
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1402085745
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: 1402086520
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: 6611674829
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: 9781402085741
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: 9781402086526
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: 9786611674823
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| Bibliographies/Indexes
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Includes bibliographical references and index
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| Contents
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Cover -- Copyright -- Dedication -- TOC$Contents -- Foreword -- Preface -- CH$1. Introduction -- 1.1 Challenge: From Board to SoC -- 1.2 Degrees of SoC Customization -- 1.2.1 Computation -- 1.2.2 Communication -- 1.3 Organization of this Book -- CH$2. SoC Design Methodologies -- 2.1 Traditional HW/SW Co-Design -- 2.1.1 HW/SW Co-Simulation -- 2.1.2 Automatic Synthesis -- 2.2 System Level Design -- 2.2.1 Motivation -- 2.2.2 Standardization -- 2.2.3 Design Flows -- 2.3 Current Research on SoC Design Methodologies -- 2.3.1 Bottom-Up SoC Design -- 2.3.2 Top-Down SoC Design -- 2.4 Contribution of this Work -- CH$3. Communication Modeling -- 3.1 Transaction Level Modeling -- 3.1.1 Use Cases -- 3.1.2 Abstraction Levels -- 3.2 Generic Communication Modeling -- 3.2.1 Architects View Framework (AVF) -- 3.2.2 Generic TLM Simulation Modules -- 3.3 Communication Customization -- 3.3.1 Communication IP Providers -- 3.3.2 Protocol Specific TLM Interfaces -- 3.4 The BusCompiler Tool -- 3.4.1 Cycle Accurate Communication Modeling -- 3.4.2 BusCompiler Input Specification -- CH$4. Processor Modeling -- 4.1 Generic Processor Modeling -- 4.1.1 Native Execution on the Simulation Host -- 4.1.2 Generic Assembly Level -- 4.2 Processor Customization Techniques -- 4.2.1 Selectable Processor Core IP -- 4.2.2 (Re-)Configurable Processor Architectures -- 4.2.3 ADLs -- 4.3 LISA -- 4.3.1 LISA Processor Design Platform -- 4.3.2 Abstraction Levels -- 4.3.3 LISA 2.0 Input Specification -- CH$5. Processor System Integration -- 5.1 Simulator Structure -- 5.1.1 Standalone Processor Simulator -- 5.1.2 The LISA Bus Interface -- 5.1.3 SystemC Wrapper -- 5.2 Adaptors: Bridging Abstraction Gaps -- 5.2.1 LISA Bus/Memory API -- 5.2.2 TLM Communication Module API -- 5.2.3 API Mapping -- 5.2.4 Bus Interface State Machine -- 5.3 Commercial SoC Simulation Environments -- 5.3.1 CoWare PlatformArchitect System Simulator -- 5.3.2 Synopsys SystemStudio SoC Simulator -- CH$6. Sucessive Top-Down Refinement Flow -- 6.1 Phase 1: Standalone -- 6.1.1 SoC Communication -- 6.1.2 LISA Standalone -- 6.2 Phase 2: IA ASIPAVF Communication Models -- 6.3 Phase 3: IA ASIPCA TLM Bus -- 6.4 Phase 4: CA ASIPCA TLM Bus -- 6.5 Phase 5: BCA ASIPCA TLM Bus -- 6.6 Phase 6: RTL ASIPCA TLM Bus 78 -- 6.7 Phase 7: RTL ASIPRTL Bus -- CH$7. Automatic Retargetability -- 7.1 MP-SoC Simulator Generation Chain -- 7.2 Structure of the Generated Simulator -- 7.2.1 Creating the Communication Infrastructure -- 7.2.2 Generating SystemC Processor Models -- 7.2.3 Generating Adaptors -- 7.3 Bus Interface Specification -- 7.3.1 Overview -- 7.3.2 Feeding Data into the State Machine -- 7.3.3 Characterizing the State Machine -- 7.3.4 Getting Data Out of the State Machine -- 7.3.5 Advantages -- CH$8. Debugging and Profiling -- 8.1 Multi-Processor Debugger -- 8.1.1 Retargetable Standalone Simulation -- 8.1.2 Multi-Processor Synchronization -- 8.1.3 Dynamic Connect -- 8.1.4 Source Code Level Debugging with GNU gdb -- 8.2 TLM Bus Traffic Visualization -- 8.2.1 Message Sequence Charts (MSC) -- 8.2.2 Word Level Data Display -- 8.3 Bus Interface Analysis -- 8.3.1 CoWare PlatformArchitect Analysis -- 8
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| Abstract
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The ever increasing complexity of modern electronic devices together with the continually shrinking time-to-market and product lifetimes pose enormous chip design challenges to meet flexibility, performance and energy efficiency constraints. As a consequence, the current trend is towards programmable platforms (Multi-Processor System-on-Chip Platforms, MP-SoC), which are tailored to the respective target application. In the usual case, a new platform is designed by selecting and assembling standard platform elements. However, best results can only be achieved if the processor cores and the communication modules themselves are also optimized for the target application. Effective exploration is only possible if accurate module simulators are generated automatically based on abstract specifications. As a matter of fact, CoWarea (TM)s BusCompiler allows generating accurate simulators for communication modules, and modeling languages such as LISA enable the same for processor cores. In Retargetable Processor System Integration into Multi-Processor System-on-Chip Platforms, such originally independent approaches are combined in order to enable the development of highly optimized programmable platforms. The first chapters of this book summarize the state of the art in all three involved fields separately: general system level design, communication modeling, and processor modeling. The main chapters then present a methodology and the associated tooling for enabling design space exploration as well as a successive refinement flow for the design of optimized MP-SoCs with a high degree of automation
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| Subject
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Multiprocessors
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Systems on a chip
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| LC Classification
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QA76.5eb
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| Added Entry
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Leupers, Rainer
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Meyr, Heinrich
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