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" Logic minimization algorithms for VLSI synthesis / "


Document Type : BL
Record Number : 698247
Doc. No : b520436
Title & Author : Logic minimization algorithms for VLSI synthesis /\ by Robert K. Brayton ... [et al.]
Publication Statement : Boston :: Kluwer Academic Publishers,, c1984
Series Statement : The Kluwer international series in engineering and computer science ;; SECS 2.VLSI, computer architecture, and digital signal processing
Page. NO : ix, 193 p. :: ill. ;; 25 cm
ISBN : 0898381649
Notes : Includes index
Bibliographies/Indexes : Bibliography: p. [174]-190
Subject : Algorithms
Subject : Integrated circuits-- Design and construction-- Data processing
Subject : Integrated circuits-- Very large scale integration
Subject : Logic design
LC Classification : ‭TK7868.L6‬‭L626 1984‬
Added Entry : Brayton, Robert King
copyhttps://lib.clisel.com/site/catalogue/698247
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