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" Integrated circuit and system design : "
Jorge Juan Chico, Enrico Macii, eds.
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BL
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746041
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b565990
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| Main Entry
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Jorge Juan Chico, Enrico Macii, eds.
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| Title & Author
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Integrated circuit and system design : : power and timing modeling, optimization and simulation : 13th International Workshop, PATMOS 2003, Turin, Italy, September 10-12, 2003 : proceedings\ Jorge Juan Chico, Enrico Macii, eds.
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| Publication Statement
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Berlin ; New York : Springer, ©2003.
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| Series Statement
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Lecture notes in computer science, 2799.
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(xvii, 631 pages) : illustrations
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| ISBN
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3540397620
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: 9783540397625
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| Contents
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Keynote Speech --; Architectural Challenges for the Next Decade Integrated Platforms --; Gate-Level Modeling and Design --; Analysis of High-Speed Logic Families --; Low Voltage, Double-Edge-Triggered Flip Flop --; A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems --; State Encoding for Low-Power FSMs in FPGA --; Low Level Modeling and Characterization --; Reduced Leverage of Dual Supply Voltages in Ultra Deep Submicron Technologies --; A Compact Charge-Based Crosstalk Induced Delay Model for Submicronic CMOS Gates --; CMOS Gate Sizing under Delay Constraint --; Process Characterisation for Low VTH and Low Power Design --; Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental Results --; Interconnect Modeling and Optimization --; Effects of Temperature in Deep-Submicron Global Interconnect Optimization --; Interconnect Parasitic Extraction Tool for Radio-Frequency Integrated Circuits --; Estimation of Crosstalk Noise for On-Chip Buses --; A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization --; Interconnect Driven Low Power High-Level Synthesis --; Asynchronous Techniques --; Bridging Clock Domains by Synchronizing the Mice in the Mousetrap --; Power-Consumption Reduction in Asynchronous Circuits Using Delay Path Unequalization --; New GALS Technique for Datapath Architectures --; Power/Area Tradeoffs in 1-of-M Parallel-Prefix Asynchronous Adders --; Static Implementation of QDI Asynchronous Primitives --; Keynote Speech --; The Emergence of Design for Energy Efficiency: An EDA Perspective --; Industrial Session --; The Most Complete Mixed-Signal Simulation Solution with ADVance MS --; Signal Integrity and Power Supply Network Analysis of Deep SubMicron Chips --; Power Management in Synopsys Galaxy Design Platform --; Open Multimedia Platform for Next-Generation Mobile Devices --; RTL Power Modeling and Memory Optimisation --; Statistical Power Estimation of Behavioral Descriptions --; A Statistical Power Model for Non-synthetic RTL Operators --; Energy Efficient Register Renaming --; Stand-by Power Reduction for Storage Circuits --; A Unified Framework for Power-Aware Design of Embedded Systems --; High-Level Modeling --; A Flexible Framework for Fast Multi-objective Design Space Exploration of Embedded Systems --; High-Level Area and Current Estimation --; Switching Activity Estimation in Non-linear Architectures --; Instruction Level Energy Modeling for Pipelined Processors --; Power Estimation Approach of Dynamic Data Storage on a Hardware Software Boundary Level --; Power Efficient Technologies and Designs --; An Adiabatic Charge Pump Based Charge Recycling Design Style --; Reduction of the Energy Consumption in Adiabatic Gates by Optimal Transistor Sizing --; Low-Power Response Time Accelerator with Full Resolution for LCD Panel --; Memory Compaction and Power Optimization for Wavelet-Based Coders --; Design Space Exploration and Trade-Offs in Analog Amplifier Design --; Keynote Speech --; Power and Timing Driven Physical Design Automation --; Communication Modeling and Design --; Analysis of Energy Consumed by Secure Session Negotiation Protocols in Wireless Networks --; Remote Power Control of Wireless Network Interfaces --; Architecture-Driven Voltage Scaling for High-Throughput Turbo-Decoders --; A Fully Digital Numerical-Controlled-Oscillator --; Low Power Issues in Processors and Multimedia --; Energy Optimization of High-Performance Circuits --; Instruction Buffering Exploration for Low Energy Embedded Processors --; Power-Aware Branch Predictor Update for High-Performance Processors --; Power Optimization Methodology for Multimedia Applications Implementation on Reconfigurable Platforms --; High-Level Algorithmic Complexity Analysis for the Implementation of a Motion-JPEG2000 Encoder --; Poster Session 1 --; Metric Definition for Circuit Speed Optimization --; Optical versus Electrical Interconnections for Clock Distribution Networks in New VLSI Technologies --; An Asynchronous Viterbi Decoder for Low-Power Applications --; Analysis of the Contribution of Interconnect Effects in Energy Dissipation of VLSI Circuits --; A New Hybrid CBL-CMOS Cell for Optimum Noise/Power Application --; Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits --; Poster Session 2 --; A Practical ASIC Methodology for Flexible Clock Tree Synthesis with Routing Blockages --; Frequent Value Cache for Low-Power Asynchronous Dual-Rail Bus --; Reducing Static Energy of Cache Memories via Prediction-Table-Less Way Prediction --; A Bottom-Up Approach to On-Chip Signal Integrity --; Advanced Cell Modeling Techniques Based on Polynomial Expressions --; RTL-Based Signal Statistics Calculation Facilitates Low Power Design Approaches --; Poster Session 3 --; Data Dependences Critical Path Evaluation at C/C++ System Level Description --; A Hardware/Software Partitioning and Scheduling Approach for Embedded Systems with Low-Power and High Performance Requirements --; Consideration of Control System and Memory Contributions in Practical Resource-Constrained Scheduling for Low Power --; Low-Power Cache with Successive Tag Comparison Algorithm --; FPGA Architecture Design and Toolset for Logic Implementation --; Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis.
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| Abstract
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This book constitutes the refereed proceedings of the 13th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2003, held in Torino, Italy in September 2003. The 43 revised full papers and 18 revised poster papers presented together with three keynote contributions were carefully reviewed and selected from 85 submissions. The papers are organized in topical sections on gate-level modeling and characterization, interconnect modeling and optimization, asynchronous techniques, RTL power modeling and memory optimization, high-level modeling, power-efficient technologies and designs, communication modeling and design, and low-power issues in processors and multimedia.
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| Subject
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Integrated circuits -- Very large scale integration -- Computer-aided design -- Congresses.
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| Subject
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Integrated circuits -- Very large scale integration -- Computer-aided design.
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| Added Entry
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Enrico Macii
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Jorge Juan Chico
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