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" Algorithm-architecture matching for signal and image processing : "
Guy Gogniat ... eds.
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BL
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| Record Number
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772158
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b592151
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| Main Entry
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Guy Gogniat ... eds.
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| Title & Author
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Algorithm-architecture matching for signal and image processing : : best papers from design and architectures for signal and image processing 2007 et 2008 et 2009\ Guy Gogniat ... eds.
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| Publication Statement
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Dordrecht : Springer, 2011
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| Series Statement
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Lecture notes in electrical engineering, 73.
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| ISBN
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9048199646
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: 9048199654
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: 9789048199648
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: 9789048199655
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| Contents
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Preface. Part 1: Architectures for embedded applications. Chapter 1: Architectures for image processing. Lossless Multi-mode Interband Image Compression and its Hardware Architecture. Efficient Memory Management for Uniform and Recursive Grid Traversal. Chapter 2: Architectures for signal and telecommunication processing. Mapping a Telecommunication Application on a Multiprocessor System-on-Chip. Part 2: Data acquisition and embedded systems. Chapter 3: Sensors for data acquisition. A Standard 3.5T CMOS Imager including a Light Adaptive System for Integration Time Optimization. Chapter 4: Operators for embedded systems. Approximate Multiplication and Division for Arithmetic Data Value Speculation in a RISC Processor. Chapter 5: Partial and dynamic reconfiguration for signal and image processing. RANN: A Reconfigurable Artificial Neural Network Model for Task Scheduling on Reconfigurable System-on-Chip. A New three-Level Strategy for Off-line Placement of Hardware Tasks on Partially and Dynamically Reconfigurable Hardware. End-to-end Bitstreams Repository Hierarchy for FPGA Partially Reconfigurable Systems. Part 3: Embedded systems design. Chapter 6: RTOS for embedded systems. SystemC multiprocessor RTOS model for services distribution on MPSoC platforms. Chapter 7: Scheduling of embedded systems. A List Scheduling Heuristic with New Node Priorities and Critical Child Technique for Task Scheduling with Communication Contention. Multiprocessor scheduling of dataflow programs within the Reconfigurable Video Coding framework. Chapter 8: CAD tools for signal and image processing. A High Level Synthesis Flow Using Model Driven Engineering. Generation of Hardware/Software systems based on CAL dataflow description.
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| LC Classification
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TK7895.E42G894 2011
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| Added Entry
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Guy Gogniat
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