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" Planar Processing Primer "
by George E. Anner.
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BL
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772378
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b592372
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| Main Entry
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by George E. Anner.
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Planar Processing Primer\ by George E. Anner.
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| Publication Statement
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Dordrecht : Springer Netherlands, 1990
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| ISBN
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940090441X
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: 9401066825
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: 9789400904415
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: 9789401066822
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| Contents
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1. Planar Processing and Basic Devices --; 2. Wafers --; 3. Wafer Measurements --; 4. Equilibrium Concepts --; 5. Oxidation --; 6. Diffusion: Predeposition --; 7. Diffusion; Redistribution --; 8. Ion Implantation --; 9. Chemical Vapor Deposition; Epitaxy --; 10. Etching --; 11. Lithography --; 12. Physical Vapor Deposition; Sputtering --; Appendix A. Four-Point-Probe Derivations; Optical Interference --; A.1 Semi-Infinite (S-I) Sample --; A.2 Thickness Correction for l-t Samples --; A.3 Logarithmic Potential Derivation for Thin Samples --; A.4 Optical Interference --; Appendix B. Ion/Field Interactions --; Appendix C. The Glow Discharge --; C.1 General Gas Discharge --; C.2 The Glow --; C.3 A-C/R-F Glow Discharge --; C.4 R-F Problems --; C.5 Modified Techniques --; Appendix D. Gas Systems --; D.1 Basic Concepts --; D.2 Conductance Calculations --; D.3 Gas Supply Systems --; D.4 Gas Distribution Systems --; D.5 Exhaust Pump Considerations --; F.5.4. Dry Oxidation Curves for (111) Silicon Showing the Effect of Oxidant Pressure --; F.5.5. Dry Oxidation Curves of (111) Silicon with Added Chlorides --; F.5.6. Wet Oxidation of (111) Silicon and Silicon Nitride --; F.5.7. MBASIC Program for Oxidation of Silicon at Atmospheric Pressure --; F.6.1. Diffusion Data --; F.6.2. Error Function Properties --; F.6.3. Error Function Table --; F.6.5. Irvin Sheet Resistance Curves --; F.6.6. Oxide Masking Curves for Boron Predep --; F.6.7. Oxide Masking Curves for Phosphorus Predep --; F.6.8. Vapor Pressure Curves of Liquid Predep Sources --; F.6.10 Boron Nitride Predep Curves --; F.8.1. Ion Implantation: Effective Range Data --; Appendix G. Numerical Constants --; Appendix H. Furnace Construction.
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| Abstract
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Planar Processing Primer is based on lecture notes for a silicon planar process ing lecture/lab course offered at the University of Illinois-UC for over fifteen years. Directed primarily to electrical engineering upperclassmen and graduate students, the material also has been used successfully by graduate students in physics and ceramic and metallurgical engineering. It is suitable for self-study by engineers trained in other disciplines who are beginning work in the semiconductor fields, and it can make circuit design engineers aware of the processing limitations under which they must work. The text describes and explains, at an introductory level, the principal processing steps used to convert raw silicon into a semiconductor device or integrated circuit. First-order models are used for theoretical treatments (e.g., of diffusion and ion implantation), with reference made to more advanced treatments, to computer programs such as SUPREM that include higher order effects, and to interactions among sequential processes. In Chapters 8, 9, and to, the application of silicon processes to compound semiconductors is discussed briefly. Over the past several years, the size of transistors has decreased markedly, allowing more transistors per chip unit area, and chip size has increased.
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Science (General)
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| LC Classification
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TK7871.85B944 1990
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| Added Entry
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George E Anner
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