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" Adaptive Analog VLSI Neural Systems "
by M.A. Jabri, R.J. Coggins, B.G. Flower.
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BL
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| Record Number
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775661
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b595657
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| Main Entry
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by M.A. Jabri, R.J. Coggins, B.G. Flower.
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| Title & Author
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Adaptive Analog VLSI Neural Systems\ by M.A. Jabri, R.J. Coggins, B.G. Flower.
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| Publication Statement
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Dordrecht : Springer Netherlands, 1996
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| Page. NO
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(vii, 262 pages)
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| ISBN
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9401105251
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: 9789401105255
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| Contents
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1 Overview --; Book roadmap --; Acknowledgements --; 2 Introduction to neural computing --; 2.1 Introduction --; 2.2 Framework --; 2.3 Learning --; 2.4 Perceptrons --; 2.5 The Multi-Layer Perceptron --; 2.6 The back-propagation algorithm --; 2.7 Comments --; 3 MOS devices and circuits --; 3.1 Introduction --; 3.2 Basic properties of MOS devices --; 3.3 Conduction in MOSFETs --; 3.4 Complementary MOSFETs --; 3.5 Noise in MOSFETs --; 3.6 Circuit models of MOSFETs --; 3.7 Simple CMOS amplifiers --; 3.8 Multistage op amps --; 3.9 Choice of amplifiers --; 3.10 Data converters --; 4 Analog VLSI building blocks --; 4.1 Functional designs to architectures --; 4.2 Neurons and synapses --; 4.3 Layout strategies --; 4.4 Simulation strategies --; 5 Kakadu --; a micropower neural network --; 5.1 Advantages of analog implementation --; 5.2 Architecture --; 5.3 Implementation --; 5.4 Chip testing --; 5.5 Discussion --; 6 Supervised learning in an analog framework --; 6.1 Introduction --; 6.2 Learning in an analog framework --; 6.3 Notation --; 6.4 Weight update strategies --; 6.5 Learning algorithms --; 6.6 Credit assignment efficiency --; 6.7 Parallelization heuristics --; 6.8 Experimental methods --; 6.9 ICEG experimental results --; 6.10 Parity 4 experimental results --; 6.11 Discussion --; 6.12 Conclusions --; 7 A micropower intracardiac electrogram classifier --; 7.1 Introduction --; 7.2 Architecture --; 7.3 Training system --; 7.4 Classification performance and power consumption --; 7.5 Discussion --; 7.6 Conclusion --; 8 On-chip perturbation based learning --; 8.1 Introduction --; 8.2 On-chip learning multi-layer perceptron --; 8.3 On-chip learning recurrent neural network --; 8.4 Conclusion --; 9 An analog memory technique --; 9.1 Introduction --; 9.2 Self-refreshing storage cells --; 9.3 Multiplying DACs --; 9.4 A/D-D/A static storage cell --; 9.5 Basic principle of the storage cell --; 9.6 Circuit limitations --; 9.7 Layout considerations --; 9.8 Simulation results --; 9.9 Discussion --; 10 Switched capacitor techniques --; 10.1 A charge-based network --; 10.2 Variable gain, linear, switched capacitor neurons --; 11 A high speed image understanding system --; 11.1 Introduction --; 11.2 The NET32K chip --; 11.3 The NET32K board system --; 11.4 Applications --; 11.5 Summary and conclusions --; 12 A Boltzmann learning system --; 12.1 Introduction --; 12.2 The Boltzmann machine --; 12.3 Deterministic learning by error propagation --; 12.4 Mean-field version of Boltzmann machine --; 12.5 Electronic implementation of a Boltzmann machine --; 12.6 Building a system using the learning chips --; 12.7 Other applications --; References.
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| Abstract
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This book approaches VLSI neural networks from a practical viewpoint, using case studies to show the full process of VLSI implementation of a network, and addressing the important issues of learning algorithms and limited precision effects. System aspects and low-power implementation issues are also covered. The authors are all international figures in the field from AT & T Bell Labs, Bellcore and SEDAL.
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Computer engineering.
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Computer science.
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Engineering.
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| LC Classification
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QA76.87B963 1996
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| Added Entry
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B G Flower
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M A Jabri
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R J Coggins
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