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" Mitigation of Thermally Induced Soft Errors in CMOS Nanoscale Circuits "
Md. Sofikul Islam
Sayil, Selahattin
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Latin Dissertation
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| Language of Document
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English
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| Record Number
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805137
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| Doc. No
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TL49986
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| Call number
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2150238534; 10743575
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| Main Entry
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Polat, Kazim Gurkan
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| Title & Author
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Mitigation of Thermally Induced Soft Errors in CMOS Nanoscale Circuits\ Md. Sofikul IslamSayil, Selahattin
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| College
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Lamar University - Beaumont
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| Date
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2017
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| Degree
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D.E.
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| field of study
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Electrical Engineering
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| student score
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2017
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| Page No
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122
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| Note
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Committee members: Liu, Jiangjiang; Tcheslavski, Gleb; Wang, Ruhai
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| Note
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Place of publication: United States, Ann Arbor; ISBN=978-0-438-69848-2
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| Abstract
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As technology advances, the semiconductor industry faces signal integrity challenges. One major concern is the radiation-induced soft errors in complementary metal oxide semiconductor (CMOS) combinational logic circuits due to the continuous scale down of feature size. As supply voltages and node capacitances are reduced, circuits become much more susceptible to radiation because node critical charge decreases. This work reports that increasing circuit temperature deteriorates circuit reliability and further increases Single Event Transient (SET) effects. Increased temperature affects the driving strength of transistors by increasing driver resistance. Therefore, if thermal impact is not considered properly, standard measures such as driver sizing may fail as temperature increases, causing a new reliability issue. Moreover, using only driver sizing technique to mitigate thermal impact on SET is not proficient because there will be greater area penalty. This work first discusses the effects of temperature on SET and then proposes a mitigation method for thermally-induced SET based on parallel circuit technique including a temperature sensor. The simulation herein shows that parallel circuit technique reduces area penalty to 18.62% for P-hit and 16.23% for N-hit, and the delay can be decreased a maximum of ~8% in the critical path compared to typical driver sizing method.
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| Subject
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Electrical engineering
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| Descriptor
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Applied sciences;CMOS circuits;Parallel circuit technique;SET effects;Thermal effect
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| Added Entry
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Sayil, Selahattin
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| Added Entry
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Electrical EngineeringLamar University - Beaumont
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