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" RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design / "


Document Type : BL
Record Number : 853010
Main Entry : Sutherland, Stuart,1953-
Title & Author : RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design /\ Stuart Sutherland.
Publication Statement : Tualatin, OR :: Sutherland HDL, Inc.,, [2017]
: , ©2017
Page. NO : xxxi, 453 pages :: illustrations ;; 23 cm
ISBN : 1546776346
: : 9781546776345
Bibliographies/Indexes : Includes bibliographical references and index.
Subject : Computer simulation.
Subject : Electronic digital computers-- Design and construction.
Subject : Verilog (Computer hardware description language)
Subject : Computer simulation.
Subject : Electronic digital computers-- Design and construction.
Subject : Verilog (Computer hardware description language)
Dewey Classification : ‭621.392‬
LC Classification : ‭TK7885.7‬‭.S874 2017‬
Parallel Title : RTL modeling with System Verilog for simulation and synthesis using System Verilog for ASIC and FPGA design
copyhttps://lib.clisel.com/site/catalogue/853010
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