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BL
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| Record Number
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861485
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| Main Entry
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Santos, Mauro
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| Title & Author
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Logarithmic voltage-to-time converter for analog-to-digital signal conversion /\ Mauro Santos, Jorge Guilherme, Nuno Horta.
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| Publication Statement
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Cham, Switzerland :: Springer Nature :: Springer,, [2019]
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| Series Statement
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Lecture notes in electrical engineering ;; volume 558
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| Page. NO
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1 online resource (xxi, 117 pages) :: illustrations (some color)
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| ISBN
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3030159787
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: 9783030159788
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3030159779
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9783030159771
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9783030159801
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| Bibliographies/Indexes
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Includes bibliographical references.
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| Contents
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Intro; Preface; Contents; Abbreviations; List of Figures; List of Tables; Keywords; 1 Introduction; 1.1 Nonlinear Data Conversion; 1.2 Motivation; 1.3 Research Goals; 1.4 Innovative Contributions; 1.5 Document Structure; References; 2 Nonlinear A/D Converters; 2.1 Floating Point Converters; 2.2 Logarithmic Converters; 2.2.1 Logarithmic Pipeline Converters; 2.2.2 Two-Step Logarithmic Converters; 2.3 Piecewise Linear Converters; 2.4 Oversampled Converters; 2.4.1 Delta Converters; 2.4.2 Sigma-Delta Converters; 2.5 Nonlinear Conversion Using Pulse Width Modulation; 2.5.1 Modified Integrating ADC
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2.5.2 PWM Average Approximation2.6 Nonlinear Conversion Using a Lookup Table; 2.7 Other Architectures; 2.8 Performance Metrics and Converter Testing; 2.9 Conclusions; References; 3 Logarithmic ADC; 3.1 Proposed Logarithmic ADC Architecture; 3.2 Voltage-to-Time Conversion Element; 3.3 Regeneration Detection; 3.4 Sources of Nonlinearity; 3.4.1 Offset; 3.4.2 S3 Switch Resistance; 3.4.3 Regeneration Detection Circuitry; 3.4.4 Thermal Noise; 3.5 Architecture Variants; 3.5.1 Multiple Simultaneous Conversions; 3.5.2 Polarity and Magnitude Independent Conversion; 3.6 Time-to-Digital Converter
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3.7 ConclusionsReferences; 4 Logarithmic VTC Design; 4.1 Determination of Key Design Parameters; 4.1.1 Sampling Capacitors; 4.1.2 Total Transconductance; 4.1.3 Degeneration Resistors; 4.1.4 Sampling Switches; 4.1.5 Regeneration Detection; 4.2 Simulaton Results; 4.2.1 Process Variations; 4.2.2 Input Referred Noise and Offset; 4.3 Conclusions; Reference; 5 Circuit and Layout Level Validation; 5.1 Configuration Chain; 5.2 Frequency Divider; 5.3 Frequency Output Pad; 5.4 Voltage-to-Time Conversion Elements; 5.5 Phase Generator; 5.6 Programmable Delay Block
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5.7 Common Mode Voltage Effect on the Regeneration Detection Voltage5.8 Demonstrator Integrated Circuit Layout; 5.9 Simulation Results; 5.10 Conclusions; 6 Evaluation of the Prototype; 6.1 Test Platform; 6.2 Test Description; 6.3 Experimental Results; 6.3.1 Performance Comparison; 6.4 Input Range Limitation; 6.5 Conclusions; References; 7 Future Work and Conclusions; 7.1 Conclusions; 7.2 Future Work; 7.2.1 Calibration; 7.3 Improved Conversion Method; References
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| Abstract
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This book presents a novel logarithmic conversion architecture based on cross-coupled inverter. An overview of the current state of the art of logarithmic converters is given where most conventional logarithmic analog-to-digital converter architectures are derived or adapted from linear analog-to-digital converter architectures, implying the use of analog building blocks such as amplifiers. The conversion architecture proposed in this book differs from the conventional logarithmic architectures. Future possible studies on integrating calibration in the voltage to time conversion element and work on an improved conversion architecture derived from the architecture are also presented in this book.
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| Subject
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Electronic circuit design.
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Power electronics-- Design and construction.
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Electronic circuit design.
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Power electronics-- Design and construction.
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TECHNOLOGY ENGINEERING-- Mechanical.
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| Dewey Classification
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621.31/7
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| LC Classification
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TK7881.15.S26 2019
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| Added Entry
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Guilherme, Jorge
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Horta, Nuno
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