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BL
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| Record Number
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865099
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| Main Entry
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Shim, Seongbo
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| Title & Author
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Physical design and mask synthesis for directed self-assembly lithography /\ Seongbo Shim, Youngsoo Shin.
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| Publication Statement
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Cham, Switzerland :: Springer,, 2018.
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| Series Statement
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NanoScience and technology,
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| Page. NO
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1 online resource (xiv, 138 pages) :: illustrations (some color)
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| ISBN
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331976294X
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: 9783319762944
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3319762931
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9783319762937
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| Bibliographies/Indexes
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Includes bibliographical references and index.
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| Contents
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Intro; Preface; Contents; Acronyms; 1. Introduction; 1.1. Optical Lithography; 1.2. Next Generation Lithography Technologies; 1.2.1. Extreme Ultraviolet Lithography (EUVL); 1.2.2. Electron Beam Lithography (EBL); 1.2.3. Nanoimprint Lithography (NIL); 1.3. Directed Self-Assembly Lithography (DSAL); 1.4. Overview of the Book; References; Part I. Physical Design Optimizations; 2. DSAL Manufacturability; 2.1. DSA Defect; 2.1.1. DSAL for IC Design and Fabrication; 2.1.2. Lithography-Induced DSA Defect; 2.2. DSA Defect Probability; 2.2.1. Definition; 2.2.2. Defect Probability Computation.
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2.3. Experimental Observations; 2.4. Summary; References; 3. Placement Optimization for DSAL; 3.1. Introduction; 3.2. Defect Probability of Cell Pair; 3.3. Post-Placement Optimization; 3.3.1. Cell Flipping; 3.3.2. Cell Swapping and Flipping; 3.4. Automatic Placement; 3.4.1. Implementation of Placer; 3.4.2. Considerations on Analytical Placer; 3.5. Experiments; 3.6. Summary; References; 4. Post-Placement Optimization for MP-DSAL Compliant Layout; 4.1. Introduction; 4.2. MP-DSAL Decomposition; 4.3. Post-Placement Optimization; 4.3.1. MP-DSAL Decomposition of Standard Cells.
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4.3.2. Placement Optimization for Cell Row; 4.3.3. Considerations of Interrow Conflict; 4.4. Experiments; 4.5. Summary; References; 5. Redundant Via Insertion for DSAL; 5.1. Introduction; 5.2. Preliminaries; 5.2.1. Defect Probability of Via Cluster; 5.2.2. Basic Redundant Via Insertion; 5.3. DSAL Redundant Via Insertion Algorithm; 5.3.1. Graph Modeling; 5.3.2. Heuristic Insertion Algorithm; 5.4. Experiments; 5.5. Summary; References; 6. Redundant Via Insertion for MP-DSAL; 6.1. Introduction; 6.2. Simultaneous Optimization of Redundant Via and Via Cluster; 6.2.1. ILP Formulation; 6.2.2. Graph-Based Heuristic.
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6.3. Experiments; 6.4. Summary; References; Part II. Mask Synthesis and Optimizations; 7. DSAL Mask Synthesis; 7.1. Introduction; 7.2. Inverse DSA; 7.2.1. Numerical Results; 7.3. Inverse Lithography; 7.3.1. Approximation of Cost Gradient; 7.3.2. Evaluation; 7.4. Mask Design with Process Variations; 7.4.1. Inverse DSA and Inverse Lithography; 7.4.2. Insertion of DSA-Aware Assist Feature; 7.4.3. Assessment; 7.5. Summary; References; 8. Verification of Guide Patterns; 8.1. Introduction; 8.2. Test GPs; 8.2.1. Preparation of GPs; 8.2.2. Evaluation of GP Coverage; 8.3. Preparing a GP Using Geometric Parameters.
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8.3.1. Geometric Parameters; 8.3.2. Principal Component Analysis; 8.3.3. Experimental Observations; 8.4. Constructing a Verification Function; 8.5. Experimental Assessment; 8.5.1. Choice of Parameters; 8.5.2. Parameter Reduction; 8.5.3. Comparison of GP Verification Methods; 8.5.4. A Global Verification Function; 8.6. Conclusions; References; 9. Cut Optimization; 9.1. Introduction; 9.2. Preliminaries; 9.2.1. Critical Cut Distances in MP-DSAL; 9.2.2. Wire Extension: Impact on Circuit Timing; 9.3. MP-DSAL Cut Optimization; 9.3.1. ILP Formulation; 9.3.2. Heuristic Algorithm; 9.4. Experiments; 9.5. Conclusion.
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| Abstract
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This book discusses physical design and mask synthesis of directed self-assembly lithography (DSAL). It covers the basic background of DSAL technology, physical design optimizations such as placement and redundant via insertion, and DSAL mask synthesis as well as its verification. Directed self-assembly lithography (DSAL) is a highly promising patterning solution in sub-7nm technology.
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| Subject
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Integrated circuits-- Design and construction.
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Integrated circuits-- Masks.
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Lithography.
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Self-assembly (Chemistry)
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Circuits components.
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Electronic devices materials.
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Integrated circuits-- Design and construction.
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Integrated circuits-- Masks.
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Lithography.
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Nanotechnology.
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Precision instruments manufacture.
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Self-assembly (Chemistry)
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Semi-conductors super-conductors.
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TECHNOLOGY ENGINEERING-- Mechanical.
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| Dewey Classification
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621.3815
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| LC Classification
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TK7874
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| Added Entry
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Shin, Youngsoo
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