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BL
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| Record Number
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889439
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| Main Entry
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Lau, John H.
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| Title & Author
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Fan-out wafer-level packaging /\ John H. Lau.
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| Publication Statement
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Singapore :: Springer,, 2018.
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| Page. NO
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1 online resource (xx, 303 pages) :: illustrations (some color)
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| ISBN
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9789811088841
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: 9789811088858
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: 9789811342660
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: 9811088845
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: 9811088853
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: 9811342660
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9789811088834
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9811088837
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| Bibliographies/Indexes
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Includes bibliographical references.
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| Contents
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Intro; Preface; Acknowledgements; Contents; About the Author; 1 Patent Issues of Fan-Out Wafer-Level Packaging; 1.1 Introduction; 1.2 Functions of Semiconductor Packaging; 1.3 Level of Semiconductor Packaging; 1.4 Patents Impacting the Semiconductor Packaging; 1.4.1 Leadframe; 1.4.2 Organic Substrate with Solder Balls; 1.4.3 Fan-In Wafer-Level Packaging; 1.4.4 Fan-Out Wafer-Level Packaging; 1.5 Major Claims of Infineon's Patent; 1.6 TSMC InFO-WLP; 1.7 Fraunhofer IZM FOPLP; 1.8 Ball/Bump Pitch/Size of PBGA, fcPBGA, WLCSP, and FOWLP; 1.9 Summary and Recommendations; References.
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2 Flip Chip Technology Versus FOWLP2.1 Introduction; 2.2 Wafer Bumping; 2.2.1 C4 Bumps; 2.2.2 C2 (Cu Pillar with Solder Cap) Bumps; 2.3 Flip Chip Package Substrates; 2.3.1 Surface Laminar Circuit (SLC) Technology; 2.3.2 Integrated Thin-Film High-Density Organic Package (i-THOP); 2.3.3 Coreless Substrate; 2.3.4 Bump-on-Lead (BOL); 2.3.5 Embedded Trace Substrate (ETS); 2.4 Flip Chip Assembly; 2.4.1 Cu-to-Cu TCB Direct Bonding; 2.4.2 C4 Solder Mass Reflow; 2.4.3 C2 Solder Mass Reflow; 2.4.4 C2 TCB; 2.4.4.1 C2 TCB with Low Bonding Force; 2.4.4.2 C2 TCB with High Bonding Force.
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2.5 Underfill/Reliability2.6 Post-assembly Underfill; 2.6.1 Capillary Underfill (CUF); 2.6.2 Molded Underfill (MUF); 2.6.3 Printed Underfill; 2.6.3.1 A New Stencil Design; 2.6.3.2 Test Chip; 2.6.3.3 Test Substrates; 2.6.3.4 Flip Chip Assemblies; 2.6.3.5 Stencil Designs; 2.6.3.6 Test Matrix; 2.6.3.7 Baking Substrates; 2.6.3.8 Printing Process; 2.6.3.9 Capillary Action and Curing; 2.6.3.10 Effects of Underfill Viscosity, Thermal Enhancement, and Multiple Prints; 2.6.3.11 Cross Sections; 2.6.3.12 Underfill Filler Density; 2.6.3.13 Shearing Test; 2.7 Preassembly Underfill.
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2.8 Cu-Cu Direct Hybrid Bonding2.9 Flip Chip Technology Versus FOWLP; 2.10 Summary and Recommendations; References; 3 Fan-in Wafer-Level Packaging Versus FOWLP; 3.1 Introduction; 3.2 Fan-in Wafer-Level Packaging (WLP); 3.3 Wafer-Level Chip Scale Packages (WLCSPs); 3.4 WLCSP Test Vehicle; 3.4.1 The Chip; 3.4.2 The WLCSP; 3.4.3 WLCSP Key Process Steps; 3.5 PCB Assembly of the WLCSP; 3.6 Thermal Cycling Test of WLCSP-PCB Assembly; 3.6.1 Thermal Cycling Condition; 3.6.2 Crack Length Distribution of All Solder Joints; 3.6.3 Crack Propagation of the Corner Solder Joint.
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| Abstract
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This comprehensive guide to fan-out wafer-level packaging (FOWLP) technology compares FOWLP with flip chip and fan-in wafer-level packaging. It presents the current knowledge on these key enabling technologies for FOWLP, and discusses several packaging technologies for future trends. The Taiwan Semiconductor Manufacturing Company (TSMC) employed their InFO (integrated fan-out) technology in A10, the application processor for Apple's iPhone, in 2016, generating great excitement about FOWLP technology throughout the semiconductor packaging community. For many practicing engineers and managers, as well as scientists and researchers, essential details of FOWLP - such as the temporary bonding and de-bonding of the carrier on a reconstituted wafer/panel, epoxy molding compound (EMC) dispensing, compression molding, Cu revealing, RDL fabrication, solder ball mounting, etc. - are not well understood. Intended to help readers learn the basics of problem-solving methods and understand the trade-offs inherent in making system-level decisions quickly, this book serves as a valuable reference guide for all those faced with the challenging problems created by the ever-increasing interest in FOWLP, helps to remove roadblocks, and accelerates the design, materials, process, and manufacturing development of key enabling technologies for FOWLP.
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| Subject
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Chip scale packaging.
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Chip scale packaging.
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TECHNOLOGY ENGINEERING-- Mechanical.
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Engineering.
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Circuits and Systems.
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Nanotechnology and Microengineering.
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| Subject
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Optical and Electronic Materials.
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| Dewey Classification
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621.381/046
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| LC Classification
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TK7870.17
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