|
" Current-Mode Clocking and Synthesis Considering Low-Power and Skew "
Islam, Riadul
Guthaus, Matthew R.
| Document Type
|
:
|
Latin Dissertation
|
| Language of Document
|
:
|
English
|
| Record Number
|
:
|
896801
|
| Doc. No
|
:
|
TL1p10h16r
|
| Main Entry
|
:
|
Islam, Riadul
|
| Title & Author
|
:
|
Current-Mode Clocking and Synthesis Considering Low-Power and Skew\ Islam, RiadulGuthaus, Matthew R.
|
| Date
|
:
|
2017
|
| student score
|
:
|
2017
|
| Abstract
|
:
|
Over the past decade, power associated with the Clock Distribution Network (CDN) has played an increasingly important role in the global integrated circuit industry. Since Complementary Metal Oxide Semiconductor (CMOS) technology continues to shrink, new physical phenomena are added to device/transistor behaviour. However, less attention has been given to add more features to the interconnect materials. In order to reduce the power associated with interconnect, researchers introduced some efficient low power techniques like low-swing clock signaling, clock gating, and resonant energy recovery clocking. Another very attractive signaling scheme, namely Current-Mode (CM) signaling, can save significant power while maintaining high frequency operation. However, a true CM clocking methodology for local and global CDNs has not been explored. I propose a new paradigm for clock distribution that uses current, rather than voltage, to distribute a global clock signal with reduced power consumption. While CM signaling has been used in one-to-one signals, this is the first usage in a one-to-many CDN. To accomplish this, I create a new high-performance current-mode pulsed flipflop with enable (CMPFFE) using a representative 45nm CMOS technology. When the CMPFFE is combined with a CM transmitter, the first CM clock distribution network exhibits 45.2% lower average power compared to traditional voltage-mode (VM) clocks. In addition, I propose the first CM clock synthesis (CMCS) methodology to reduce overall clock network power with low skew. The method can integrate with traditional clock routing followed by transmitter and receiver sizing. I validate the proposed methodology using ISPD 2009 and 2010 industrial benchmarks. This methodology saves 39-84% average power with similar skew on the benchmarks using 45nm CMOS technology simulation of clock frequencies range from 1-3GHz. In addition, the CMCS methodology takes 2.4-9.1x less running time and consumes 20-26% less transistor area compared to synthesized, buffered VM clock distributions.
|
| Added Entry
|
:
|
Islam, Riadul
|
| Added Entry
|
:
|
UC Santa Cruz
|
| |