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" Optimization of the BEOL Interconnect Stack for Advanced Semiconductor Technology Nodes "
Shah, Pooja Pradeep
Kahng, Andrew B
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Latin Dissertation
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English
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897830
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TL9sf895pj
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| Main Entry
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Lin, Chen
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| Title & Author
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Optimization of the BEOL Interconnect Stack for Advanced Semiconductor Technology Nodes\ Shah, Pooja PradeepKahng, Andrew B
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2015
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2015
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| Abstract
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Particularly in advanced technology nodes, interconnects significantly affect the power, performance, area and reliability of integrated circuits. Requirements of high integration density, performance, complex patterning technology and cost implications make it imperative to determine optimal back-end-of-line (BEOL) stack dimensions for sub-22nm technology nodes. This thesis studies copper interconnect scaling strategies for high-performance IC designs. It focuses on determining optimal dimensions of the BEOL interconnect stack to achieve least possible delay while maintaining low power consumption. Degrees of freedom of the optimization technique in this work are wire aspect ratio (AR) and wire line-space duty cycle (DC).1 Our study targets the interconnect scaling strategy for 28nm through 7nm integrated device manufacturer (IDM) nodes, which have a more rigorous scaling trend than what is seen in the pure-play foundry “node” taxonomy. For example, the 14nm IDM node has a minimum Metal-1 pitch of 52nm [31], while the corresponding pitch for the pure-play foundry 14nm technology node is 64nm [39]. The studies in this thesis also indicate the advantages of using a low wire aspect ratio and a high line-space duty cycle for sub-22nm technology nodes. 1 We define AR by T/W = metal thickness / metal width, and DC using L/(L + S) = line-width / pitch.
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Shah, Pooja Pradeep
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UC San Diego
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