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" Systematic Characterization of Graphene ESD Interconnects for On-Chip ESD Protection "
Chen, QMa, RZhang, WLu, FWang, CLiang, OZhang, FLi, CTang, HXie, YHWang, A
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AL
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901071
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LA0h91h0zc
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Systematic Characterization of Graphene ESD Interconnects for On-Chip ESD Protection [Article]\ Chen, QMa, RZhang, WLu, FWang, CLiang, OZhang, FLi, CTang, HXie, YHWang, A
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2016
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UCLA
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| Abstract
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© 1963-2012 IEEE. We report systematic transient characterization of a graphene ribbon (GR) used as an interconnect for electrostatic discharge (ESD) protection of future integrated circuits. A large set of GR wires (around 6000) with varying and practical dimensions were fabricated using the chemical vapor deposition method and characterized by transmission line pulsing (TLP) and very fast TLP (VFTLP) measurements. Comprehensive TLP and VFTLP testing with varying pulse rise time (tr) and duration (td) was performed across a wide temperature range ( T = -30/+110°C). Measurement-based statistics reveal the relationship between ESD capability of GR wires and the wire length (L), width (W), and number of graphene layers, as well as ESD pulse shapes and operation temperature.
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