Design of CMOS ternary latches

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" Design of CMOS ternary latches "
Shou, X Q; Kalantari, N; Green, Michael M

Document Type	:	AL
Record Number	:	910400
Doc. No	:	LA61f754rc
Title & Author	:	Design of CMOS ternary latches [Article]\ Shou, X Q; Kalantari, N; Green, Michael M
Date	:	2006
Title of Periodical	:	UC Irvine
Abstract	:	This paper describes the design methodology of latches with three stable operating points. Open-loop analysis is used to obtain insight into how a conventional binary latch structure can be modified to yield a ternary latch. Four novel ternary latch structures, compatible with a standard CMOS process, are presented. Properties of each latch, including robustness of the ternary behavior, speed, and power dissipation, are described. Measurement results of four RS ternary flip-flops based on the proposed latch structures, fabricated in a standard 0.18-mu m CMOS process, are presented. Maximum operating frequency and skew tolerance are reported for each of the four latches.