Design and evaluation of a high throughput QoS-aware and congestion-aware router architecture for Ne...

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" Design and evaluation of a high throughput QoS-aware and congestion-aware router architecture for Network-on-Chip "
Wang, C; Bagherzadeh, N; Editor(s): Stotzka, Rainer; Schiffers, Michael; Cotronis, Yannis

Document Type	:	AL
Record Number	:	911390
Doc. No	:	LA6p176798
Title & Author	:	Design and evaluation of a high throughput QoS-aware and congestion-aware router architecture for Network-on-Chip [Article]\ Wang, C; Bagherzadeh, N; Editor(s): Stotzka, Rainer; Schiffers, Michael; Cotronis, Yannis
Date	:	2014
Title of Periodical	:	UC Irvine
Abstract	:	This paper proposes a novel QoS-aware and congestion-aware Network-on-Chip architecture that not only enables quality-oriented network transmission and maintains a feasible implementation cost but also well balance traffic load inside the network to enhance overall throughput. By differentiating application traffic into different service classes, bandwidth allocation is managed accordingly to fulfill QoS requirements. Incorporating with congestion control scheme which consists of dynamic arbitration and adaptive routing path selection, high priority traffic is directed to less congested areas and is given preference to available resources. Simulation results show that average latency of high priority and overall traffic is improved dramatically for various traffic patterns. Cost evaluation results also show that the proposed router architecture requires negligible cost overhead but provides better performance for both advanced mesh NoC platforms. © 2013 Elsevier B.V. All rights reserved.