| Document Type
|
:
|
BL
|
| Record Number
|
:
|
963179
|
| Doc. No
|
:
|
b717549
|
| Title & Author
|
:
|
VLSI test principles and architectures : : design for testability /\ edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen.
|
| Publication Statement
|
:
|
Amsterdam ;Boston :: Elsevier Morgan Kaufmann Publishers,, ©2006.
|
| Series Statement
|
:
|
The Morgan Kaufmann series in systems on silicon
|
| Page. NO
|
:
|
1 online resource (xxx, 777 pages) :: illustrations
|
| ISBN
|
:
|
0080474799
|
|
|
:
|
: 9780080474793
|
|
|
:
|
0123705975
|
|
|
:
|
9780123705976
|
| Bibliographies/Indexes
|
:
|
Includes bibliographical references and index.
|
| Contents
|
:
|
Design for testability / Laung-Terng (L.-T.) Wang, Xiaoqing Wen, and Khader S. Abdel-Hafez -- Logic and fault simulation / Jiun-Lang Huang, James C.-M. Li, and Duncan M. (Hank) Walker -- Test generation / Michael S. Hsiao -- Logic built-in self-test / Laung-Terng (L.-T.) Wang -- Test compression / Xiaowei Li, Kuen-Jong Lee, and Nur A. Touba -- Logic diagnosis / Shi-Yu Huang -- Memory testing and built-in self-test / Cheng-Wen Wu -- Memory diagnosis and built-in self-repair / Cheng-Wen Wu -- Boundary scan and core-based testing / Kuen-Jong Lee -- Analog and mixed-signal testing / Chauchin Su -- Test technology trends in the nanometer age / Kwang-Ting (Tim) Cheng, Wen-Ben Jone, and Laung-Terng (L.-T.) Wang.
|
| Abstract
|
:
|
This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. Lecture slides and exercise solutions for all chapters are now available. Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.
|
| Subject
|
:
|
Integrated circuits-- Very large scale integration-- Design.
|
| Subject
|
:
|
Integrated circuits-- Very large scale integration-- Testing.
|
| Subject
|
:
|
Circuits intégrés à très grande échelle-- Conception et construction.
|
| Subject
|
:
|
Circuits intégrés à très grande échelle-- Essais.
|
| Subject
|
:
|
Circuitos integrados vlsi.
|
| Subject
|
:
|
COMPUTERS-- Logic Design.
|
| Subject
|
:
|
Integrated circuits-- Very large scale integration-- Design.
|
| Subject
|
:
|
Integrated circuits-- Very large scale integration-- Design.
|
| Subject
|
:
|
Integrated circuits-- Very large scale integration-- Testing.
|
| Subject
|
:
|
Integrated circuits-- Very large scale integration-- Testing.
|
| Subject
|
:
|
TECHNOLOGY ENGINEERING-- Electronics-- Circuits-- Logic.
|
| Subject
|
:
|
TECHNOLOGY ENGINEERING-- Electronics-- Circuits-- VLSI ULSI.
|
| Subject
|
:
|
Testen
|
| Subject
|
:
|
VLSI
|
| Dewey Classification
|
:
|
621.39/5
|
| LC Classification
|
:
|
TK7874.75.V587 2006eb
|
| NLM classification
|
:
|
ZN 4030rvk
|
|
|
:
|
ZN 4030.rvk
|
|
|
:
|
ZN 4950rvk
|
|
|
:
|
ZN 4950.rvk
|
|
|
:
|
ZN 4952rvk
|
|
|
:
|
ZN 4952.rvk
|
| Added Entry
|
:
|
Wang, Laung-Terng
|
|
|
:
|
Wen, Xiaoqing
|
|
|
:
|
Wu, Cheng-Wen,EE Ph. D.
|