|
" IEEE standard for SystemVerilog--unified hardware design, specification, and verification language / "
sponsor, Design Automation Standards Committee of the IEEE Computer Society and the IEEE Standards Association Corporate Advisory Group.
| Document Type
|
:
|
BL
|
| Record Number
|
:
|
969567
|
| Doc. No
|
:
|
b723937
|
| Title & Author
|
:
|
IEEE standard for SystemVerilog--unified hardware design, specification, and verification language /\ sponsor, Design Automation Standards Committee of the IEEE Computer Society and the IEEE Standards Association Corporate Advisory Group.
|
| Edition Statement
|
:
|
2nd printing: 1 Feb. 2010. Correction to the Table of Contents.
|
| Publication Statement
|
:
|
New York :: Institute of Electrical and Electronics Engineers,, 2010.
|
| Page. NO
|
:
|
1 online resource (xxxvi, 1247 pages) :: illustrations
|
| ISBN
|
:
|
0738161292
|
|
|
:
|
: 9780738161297
|
| Bibliographies/Indexes
|
:
|
Includes bibliographical references (page 1247).
|
| Abstract
|
:
|
Abstract: This standard represents a merger of two previous standards: IEEE Std 1364-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document. Keywords: assertions, design automation, design verification, hardware description language, HDL, HDVL, PLI, programming language interface, SystemVerilog, Verilog, VPI.
|
| Subject
|
:
|
Computer hardware description languages-- Standards.
|
| Subject
|
:
|
Verilog (Computer hardware description language)-- Standards.
|
| Added Entry
|
:
|
IEEE Computer Society., Design Automation Standards Committee.
|
|
|
:
|
IEEE Standards Association., Corporate Advisory Group.
|
|
|
:
|
IEEE-SA Standards Board.
|
|
|
:
|
Institute of Electrical and Electronics Engineers.
|
| Parallel Title
|
:
|
IEEE standard for System Verilog--unified hardware design, specification, and verification language
|
| |